[PATCH] D54073: [x86] allow vector load narrowing with multi-use values

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: test/CodeGen/X86/avg.ll:493
 ; AVX512BW-NEXT:    retq
   %1 = load <48 x i8>, <48 x i8>* %a
   %2 = load <48 x i8>, <48 x i8>* %b
----------------
(Unrelated) We should investigate fixing this - <48 x i8> is unlikely to occur but tweaking the AVG patterns + SplitOpsAndApply to handle 'uneven split' cases should be relatively trivial.


================
Comment at: test/CodeGen/X86/avx-load-store.ll:24
 ; CHECK-NEXT:    vmovaps %ymm0, (%rbx)
-; CHECK-NEXT:    vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
+; CHECK-NEXT:    vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
 ; CHECK-NEXT:    vmovaps %ymm0, (%r15)
----------------
NFC changes - pull out?


================
Comment at: test/CodeGen/X86/avx512-extract-subvector-load-store.ll:1290
+; AVX512NOTDQ-NEXT:    movzbl 56(%rdi), %eax
+; AVX512NOTDQ-NEXT:    kmovd %eax, %k1
 ; AVX512NOTDQ-NEXT:    vpcmpeqd %ymm0, %ymm0, %ymm0
----------------
@craig.topper Is this OK?


================
Comment at: test/CodeGen/X86/insert-into-constant-vector.ll:277
+; X32AVX-NEXT:    vmovdqa {{.*#+}} ymm1 = <42,1,2,3,4,5,6,u>
+; X32AVX-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
 ; X32AVX-NEXT:    retl
----------------
This doesn't look great?


================
Comment at: test/CodeGen/X86/pr34653.ll:186
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 entry:
----------------
Codesize regression?


https://reviews.llvm.org/D54073