[PATCH] D51927: [ARM] Enable spilling of the hGPR class in Thumb2

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL346401: [ARM] Enable spilling of the hGPR register class in Thumb2 (authored by petr.pavlu, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D51927?vs=164856&id=173147#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51927

Files:
  llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/trunk/test/CodeGen/Thumb2/high-reg-spill.mir


Index: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -146,9 +146,7 @@
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
 
-  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
-      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
-      RC == &ARM::GPRnopcRegClass) {
+  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
         .addReg(SrcReg, getKillRegState(isKill))
         .addFrameIndex(FI)
@@ -190,9 +188,7 @@
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
-      RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
-      RC == &ARM::GPRnopcRegClass) {
+  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
         .addFrameIndex(FI)
         .addImm(0)
Index: llvm/trunk/test/CodeGen/Thumb2/high-reg-spill.mir
===================================================================
--- llvm/trunk/test/CodeGen/Thumb2/high-reg-spill.mir
+++ llvm/trunk/test/CodeGen/Thumb2/high-reg-spill.mir
@@ -0,0 +1,50 @@
+# RUN: llc -run-pass regallocfast %s -o - | FileCheck %s
+
+# This test examines register allocation and spilling with Fast Register
+# Allocator. The test uses inline assembler that requests an input variable to
+# be loaded in a high register but at the same time has r12 marked as clobbered.
+# The allocator initially satisfies the load request by selecting r12 but then
+# needs to spill this register when it reaches the INLINEASM instruction and
+# notices its clobber definition.
+#
+# The test checks that the compiler is able to spill a register from the hGPR
+# class in Thumb2 by inserting the t2STRi12/t2LDRi12 instructions.
+
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.c"
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv7m-none-unknown-eabi"
+
+  define dso_local void @constraint_h() {
+  entry:
+    %i = alloca i32, align 4
+    %0 = load i32, i32* %i, align 4
+    call void asm sideeffect "@ $0", "h,~{r12}"(i32 %0)
+    ret void
+  }
+
+...
+---
+name:            constraint_h
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: hgpr }
+  - { id: 1, class: tgpr }
+stack:
+  - { id: 0, name: i, size: 4, alignment: 4, stack-id: 0, local-offset: -4 }
+body:             |
+  bb.0.entry:
+    %1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
+    %0:hgpr = COPY %1
+    INLINEASM &"@ $0", 1, 589833, %0, 12, implicit-def early-clobber $r12
+    tBX_RET 14, $noreg
+
+...
+# CHECK: bb.0.entry:
+# CHECK-NEXT: renamable $r0 = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
+# CHECK-NEXT: renamable $r12 = COPY killed renamable $r0
+# CHECK-NEXT: t2STRi12 killed $r12, %stack.1, 0, 14, $noreg :: (store 4 into %stack.1)
+# CHECK-NEXT: $r8 = t2LDRi12 %stack.1, 0, 14, $noreg :: (load 4 from %stack.1)
+# CHECK-NEXT: INLINEASM &"@ $0", 1, 589833, killed renamable $r8, 12, implicit-def early-clobber $r12
+# CHECK-NEXT: tBX_RET 14, $noreg


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