[PATCH] D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:362
+  SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, Flags | RISCVII::MO_PCREL_HI);
+  SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, Flags | RISCVII::MO_LO);
+  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::AUIPC, DL, Ty, AddrHi), 0);
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jrtc27 wrote:
> This needs to be an `MO_PCREL_LO`, surely? (and then modified to refer to the `auipc` rather than the symbol...)
I was under the impression that only the `auipc` symbol needs to be PC-relative, since:
1) The upper bits are the bits we need to prevent from overflowing
2) the operation of `auipc` is to add the upper 20 bits of the symbol //relative to the program counter// to the program counter itself, putting the result into the destination register. Essentially we've done the same operation as an `lui`, but via the PC. So the `addi` should be the same?

Also more importantly I tried that and got a 'relocation truncated to fit'...

I don't quite understand what you mean by 'modified to refer to the `auipc` rather than the symbol'? Basically the first two SDValues are just building the `%pcrel_hi(sym)` & `%lo(sym)` expressions to be used in the actual sequence.


Repository:
  rL LLVM

https://reviews.llvm.org/D54143