[llvm] r346114 - [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 4 21:00:45 PST 2018
Author: dylanmckay
Date: Sun Nov 4 21:00:44 2018
New Revision: 346114
URL: http://llvm.org/viewvc/llvm-project?rev=346114&view=rev
Log:
[AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination
This is an AVR-specific workaround for a limitation of the register
allocator that only exposes itself on targets with high register
contention like AVR, which only has three pointer registers.
The three pointer registers are X, Y, and Z.
In most nontrivial functions, Y is reserved for the frame pointer,
as per the calling convention. This leaves X and Z. Some instructions,
such as LPM ("load program memory"), are only defined for the Z
register. Sometimes this just leaves X.
When the backend generates a LDDWRdPtrQ instruction with Z as the
destination pointer, it usually trips up the register allocator
with this error message:
LLVM ERROR: ran out of registers during register allocation
This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction
from ever using the Z register as an operand. This gives the
register allocator a bit more space to allocate, fixing the
regalloc exhaustion error.
Here is a description from the patch author Peter Nimmervoll
As far as I understand the problem occurs when LDDWRdPtrQ uses
the ptrdispregs register class as target register. This should work, but
the allocator can't deal with this for some reason. So from my testing,
it seams like (and I might be totally wrong on this) the allocator reserves
the Z register for the ICALL instruction and then the register class
ptrdispregs only has 1 register left and we can't use Y for source and
destination. Removing the Z register from DREGS fixes the problem but
removing Y register does not.
More information about the bug can be found on the avr-rust issue
tracker at https://github.com/avr-rust/rust/issues/37.
A bug has raised to track the removal of this workaround and a proper
fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553.
Patch by Peter Nimmervoll
Added:
llvm/trunk/test/CodeGen/AVR/rust-avr-bug-37.ll
llvm/trunk/test/CodeGen/AVR/rust-avr-bug-95.ll
Modified:
llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=346114&r1=346113&r2=346114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Sun Nov 4 21:00:44 2018
@@ -1222,7 +1222,7 @@ isReMaterializable = 1 in
// ldd Rd, P+q
// ldd Rd+1, P+q+1
let Constraints = "@earlyclobber $dst" in
- def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst),
+ def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z_WORKAROUND:$dst),
(ins memri:$memri),
"lddw\t$dst, $memri",
[(set i16:$dst, (load addr:$memri))]>,
Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td?rev=346114&r1=346113&r2=346114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td Sun Nov 4 21:00:44 2018
@@ -157,6 +157,26 @@ def DREGS : RegisterClass<"AVR", [i16],
R9R8, R7R6, R5R4, R3R2, R1R0
)>;
+// The 16-bit DREGS register class, excluding the Z pointer register.
+//
+// This is used by instructions which cause high pointer register
+// contention which leads to an assertion in the register allocator.
+//
+// There is no technical reason why instructions that use this class
+// cannot use Z; it's simply a workaround a regalloc bug.
+//
+// More information can be found in PR39553.
+def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8,
+ (
+ // Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R27R26,
+ // Callee saved registers.
+ R29R28, R17R16, R15R14, R13R12, R11R10,
+ R9R8, R7R6, R5R4, R3R2, R1R0
+ )>;
+
// 16-bit register class for immediate instructions.
def DLDREGS : RegisterClass<"AVR", [i16], 8,
(
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir?rev=346114&r1=346113&r2=346114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir Sun Nov 4 21:00:44 2018
@@ -25,11 +25,11 @@ body: |
; CHECK-LABEL: test_lddwrdptrq
- ; CHECK: ldd [[SCRATCH:r[0-9]+]], Z+10
+ ; CHECK: ldd [[SCRATCH:r[0-9]+]], Y+10
; CHECK-NEXT: push [[SCRATCH]]
- ; CHECK-NEXT: ldd [[SCRATCH]], Z+11
- ; CHECK-NEXT: mov r31, [[SCRATCH]]
- ; CHECK-NEXT: pop r30
+ ; CHECK-NEXT: ldd [[SCRATCH]], Y+11
+ ; CHECK-NEXT: mov r29, [[SCRATCH]]
+ ; CHECK-NEXT: pop r28
- early-clobber $r31r30 = LDDWRdPtrQ undef $r31r30, 10
+ early-clobber $r29r28 = LDDWRdPtrQ undef $r29r28, 10
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir?rev=346114&r1=346113&r2=346114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir Sun Nov 4 21:00:44 2018
@@ -18,8 +18,8 @@ body: |
; CHECK-LABEL: test_lddwrdptrq
- ; CHECK: ldd r30, Y+10
- ; CHECK-NEXT: ldd r31, Y+11
+ ; CHECK: ldd r28, Z+10
+ ; CHECK-NEXT: ldd r29, Z+11
- early-clobber $r31r30 = LDDWRdPtrQ undef $r29r28, 10
+ early-clobber $r29r28 = LDDWRdPtrQ undef $r31r30, 10
...
Added: llvm/trunk/test/CodeGen/AVR/rust-avr-bug-37.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/rust-avr-bug-37.ll?rev=346114&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/rust-avr-bug-37.ll (added)
+++ llvm/trunk/test/CodeGen/AVR/rust-avr-bug-37.ll Sun Nov 4 21:00:44 2018
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+%"fmt::Formatter" = type { i32, { i8*, void (i8*)** } }
+
+ at str.1b = external constant [0 x i8]
+
+define void @"TryFromIntError::Debug"(%"fmt::Formatter"* dereferenceable(32)) unnamed_addr #0 personality i32 (...)* @rust_eh_personality {
+; CHECK-LABEL: "TryFromIntError::Debug"
+start:
+ %builder = alloca i8, align 8
+ %1 = getelementptr inbounds %"fmt::Formatter", %"fmt::Formatter"* %0, i16 0, i32 1
+ %2 = bitcast { i8*, void (i8*)** }* %1 to {}**
+ %3 = load {}*, {}** %2, align 2
+ %4 = getelementptr inbounds %"fmt::Formatter", %"fmt::Formatter"* %0, i16 0, i32 1, i32 1
+ %5 = load void (i8*)**, void (i8*)*** %4, align 2
+ %6 = getelementptr inbounds void (i8*)*, void (i8*)** %5, i16 3
+ %7 = bitcast void (i8*)** %6 to i8 ({}*, i8*, i16)**
+ %8 = load i8 ({}*, i8*, i16)*, i8 ({}*, i8*, i16)** %7, align 2
+ %9 = tail call i8 %8({}* nonnull %3, i8* noalias nonnull readonly getelementptr inbounds ([0 x i8], [0 x i8]* @str.1b, i16 0, i16 0), i16 15)
+ unreachable
+}
+
+declare i32 @rust_eh_personality(...) unnamed_addr
+
+attributes #0 = { uwtable }
\ No newline at end of file
Added: llvm/trunk/test/CodeGen/AVR/rust-avr-bug-95.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/rust-avr-bug-95.ll?rev=346114&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/rust-avr-bug-95.ll (added)
+++ llvm/trunk/test/CodeGen/AVR/rust-avr-bug-95.ll Sun Nov 4 21:00:44 2018
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+%"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], { {}*, {}* }, [0 x i8], { i8*, i8* }, [0 x i8], { [0 x { i8*, i8* }]*, i16 }, [0 x i8] }
+%"option::Option<usize>.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] }
+
+ at str.4S = external constant [5 x i8]
+
+; Function Attrs: uwtable
+define void @"_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"(%"fmt::Formatter.1.77.153.229.305.381.1673"* dereferenceable(27) %__arg_0) unnamed_addr #0 personality i32 (...)* @rust_eh_personality {
+; CHECK-LABEL: "_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"
+start:
+ %0 = getelementptr inbounds %"fmt::Formatter.1.77.153.229.305.381.1673", %"fmt::Formatter.1.77.153.229.305.381.1673"* %__arg_0, i16 0, i32 11, i32 0
+ %1 = load {}*, {}** %0, align 1, !noalias !0, !nonnull !9
+ %2 = getelementptr inbounds %"fmt::Formatter.1.77.153.229.305.381.1673", %"fmt::Formatter.1.77.153.229.305.381.1673"* %__arg_0, i16 0, i32 11, i32 1
+ %3 = bitcast {}** %2 to i1 ({}*, [0 x i8]*, i16)***
+ %4 = load i1 ({}*, [0 x i8]*, i16)**, i1 ({}*, [0 x i8]*, i16)*** %3, align 1, !noalias !0, !nonnull !9
+ %5 = getelementptr inbounds i1 ({}*, [0 x i8]*, i16)*, i1 ({}*, [0 x i8]*, i16)** %4, i16 3
+ %6 = load i1 ({}*, [0 x i8]*, i16)*, i1 ({}*, [0 x i8]*, i16)** %5, align 1, !invariant.load !9, !noalias !0, !nonnull !9
+ %7 = tail call zeroext i1 %6({}* nonnull %1, [0 x i8]* noalias nonnull readonly bitcast ([5 x i8]* @str.4S to [0 x i8]*), i16 5), !noalias !10
+ unreachable
+}
+
+declare i32 @rust_eh_personality(...) unnamed_addr
+
+attributes #0 = { uwtable }
+
+!0 = !{!1, !3, !5, !6, !8}
+!1 = distinct !{!1, !2, !"_ZN3lib3fmt9Formatter9write_str17ha1a9656fc66ccbe5E: %data.0"}
+!2 = distinct !{!2, !"_ZN3lib3fmt9Formatter9write_str17ha1a9656fc66ccbe5E"}
+!3 = distinct !{!3, !4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E: argument 0"}
+!4 = distinct !{!4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E"}
+!5 = distinct !{!5, !4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E: %name.0"}
+!6 = distinct !{!6, !7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E: argument 0"}
+!7 = distinct !{!7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E"}
+!8 = distinct !{!8, !7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E: %name.0"}
+!9 = !{}
+!10 = !{!3, !6}
\ No newline at end of file
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