[llvm] r345975 - [Hexagon] Do not reduce load size for globals in small-data

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Nov  2 07:17:47 2018
New Revision: 345975

URL: http://llvm.org/viewvc/llvm-project?rev=345975&view=rev
Log:
[Hexagon] Do not reduce load size for globals in small-data

Small-data (i.e. GP-relative) loads and stores allow 16-bit scaled
offset. For a load of a value of type T, the small-data area is
equivalent to an array "T sdata[65536]". This implies that objects
of smaller sizes need to be closer to the beginning of sdata,
while larger objects may be farther away, or otherwise the offset
may be insufficient to reach it. Similarly, an object of a larger
size should not be accessed via a load of a smaller size.

Added:
    llvm/trunk/test/CodeGen/Hexagon/sdata-load-size.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=345975&r1=345974&r2=345975&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Nov  2 07:17:47 2018
@@ -3080,6 +3080,21 @@ HexagonTargetLowering::findRepresentativ
   return TargetLowering::findRepresentativeClass(TRI, VT);
 }
 
+bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load,
+      ISD::LoadExtType ExtTy, EVT NewVT) const {
+  auto *L = cast<LoadSDNode>(Load);
+  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
+  // Small-data object, do not shrink.
+  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
+    return false;
+  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
+    auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
+    const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
+    return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
+  }
+  return true;
+}
+
 Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
       AtomicOrdering Ord) const {
   BasicBlock *BB = Builder.GetInsertBlock();

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=345975&r1=345974&r2=345975&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Fri Nov  2 07:17:47 2018
@@ -304,6 +304,9 @@ namespace HexagonISD {
     SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
                                      const override;
 
+    bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
+                               EVT NewVT) const override;
+
     // Handling of atomic RMW instructions.
     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
         AtomicOrdering Ord) const override;

Added: llvm/trunk/test/CodeGen/Hexagon/sdata-load-size.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sdata-load-size.ll?rev=345975&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/sdata-load-size.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/sdata-load-size.ll Fri Nov  2 07:17:47 2018
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon -hexagon-small-data-threshold=8 < %s | FileCheck %s
+; CHECK: = memd(gp+#g0)
+; If an object will be placed in .sdata, do not shrink any references to it.
+; In this case, g0 must be loaded via memd.
+
+target triple = "hexagon"
+
+ at g0 = common global i64 0, align 8
+
+define i32 @f0() #0 {
+entry:
+  %v0 = load i64, i64* @g0, align 8
+  %v1 = trunc i64 %v0 to i8
+  %v2 = zext i8 %v1 to i32
+  ret i32 %v2
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+small-data" }
+