[llvm] r345962 - [AMDGPU] UBSan bug fix for r345710

[Neil Henning via llvm-commits]

Author: sheredom
Date: Fri Nov  2 03:24:57 2018
New Revision: 345962

URL: http://llvm.org/viewvc/llvm-project?rev=345962&view=rev
Log:
[AMDGPU] UBSan bug fix for r345710

UBSan detected an error in our ISelLowering that is exposed only when
you have a dmask == 0x1. Fix this by adding in an explicit check to
ensure we don't do the UBSan detected shl << 32.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=345962&r1=345961&r2=345962&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Fri Nov  2 03:24:57 2018
@@ -8799,7 +8799,7 @@ SDNode *SITargetLowering::adjustWritemas
 
     // Set which texture component corresponds to the lane.
     unsigned Comp;
-    for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
+    for (unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
       Comp = countTrailingZeros(Dmask);
       Dmask &= ~(1 << Comp);
     }