[llvm] r345882 - Fix clang -Wimplicit-fallthrough warnings across llvm, NFC
Reid Kleckner via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 1 12:54:46 PDT 2018
Author: rnk
Date: Thu Nov 1 12:54:45 2018
New Revision: 345882
URL: http://llvm.org/viewvc/llvm-project?rev=345882&view=rev
Log:
Fix clang -Wimplicit-fallthrough warnings across llvm, NFC
This patch should not introduce any behavior changes. It consists of
mostly one of two changes:
1. Replacing fall through comments with the LLVM_FALLTHROUGH macro
2. Inserting 'break' before falling through into a case block consisting
of only 'break'.
We were already using this warning with GCC, but its warning behaves
slightly differently. In this patch, the following differences are
relevant:
1. GCC recognizes comments that say "fall through" as annotations, clang
doesn't
2. GCC doesn't warn on "case N: foo(); default: break;", clang does
3. GCC doesn't warn when the case contains a switch, but falls through
the outer case.
I will enable the warning separately in a follow-up patch so that it can
be cleanly reverted if necessary.
Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu
Differential Revision: https://reviews.llvm.org/D53950
Modified:
llvm/trunk/include/llvm/Demangle/ItaniumDemangle.h
llvm/trunk/lib/Analysis/InlineCost.cpp
llvm/trunk/lib/Demangle/MicrosoftDemangleNodes.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Modified: llvm/trunk/include/llvm/Demangle/ItaniumDemangle.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Demangle/ItaniumDemangle.h?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Demangle/ItaniumDemangle.h (original)
+++ llvm/trunk/include/llvm/Demangle/ItaniumDemangle.h Thu Nov 1 12:54:45 2018
@@ -2807,6 +2807,7 @@ AbstractManglingParser<Derived, Alloc>::
SoFar = make<ExpandedSpecialSubstitution>(SSK);
if (!SoFar)
return nullptr;
+ break;
default:
break;
}
Modified: llvm/trunk/lib/Analysis/InlineCost.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InlineCost.cpp (original)
+++ llvm/trunk/lib/Analysis/InlineCost.cpp Thu Nov 1 12:54:45 2018
@@ -720,6 +720,7 @@ bool CallAnalyzer::visitCastInst(CastIns
case Instruction::FPToSI:
if (TTI.getFPOpCost(I.getType()) == TargetTransformInfo::TCC_Expensive)
Cost += InlineConstants::CallPenalty;
+ break;
default:
break;
}
Modified: llvm/trunk/lib/Demangle/MicrosoftDemangleNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Demangle/MicrosoftDemangleNodes.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Demangle/MicrosoftDemangleNodes.cpp (original)
+++ llvm/trunk/lib/Demangle/MicrosoftDemangleNodes.cpp Thu Nov 1 12:54:45 2018
@@ -558,6 +558,7 @@ void VariableSymbolNode::output(OutputSt
case StorageClass::PublicStatic:
case StorageClass::ProtectedStatic:
OS << "static ";
+ break;
default:
break;
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Nov 1 12:54:45 2018
@@ -351,7 +351,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_SHL:
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
- // Fall-through
+ LLVM_FALLTHROUGH;
case AMDGPU::G_FADD:
case AMDGPU::G_FPTOSI:
Modified: llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp Thu Nov 1 12:54:45 2018
@@ -236,6 +236,7 @@ R600SchedStrategy::AluKind R600SchedStra
// MI will become a KILL, don't considers it in scheduling
return AluDiscarded;
}
+ break;
default:
break;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Nov 1 12:54:45 2018
@@ -5049,12 +5049,11 @@ SDValue SITargetLowering::LowerINTRINSIC
case Intrinsic::r600_read_tgid_z:
return getPreloadedValue(DAG, *MFI, VT,
AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
- case Intrinsic::amdgcn_workitem_id_x: {
+ case Intrinsic::amdgcn_workitem_id_x:
case Intrinsic::r600_read_tidig_x:
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
SDLoc(DAG.getEntryNode()),
MFI->getArgInfo().WorkItemIDX);
- }
case Intrinsic::amdgcn_workitem_id_y:
case Intrinsic::r600_read_tidig_y:
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
Modified: llvm/trunk/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/AsmParser/BPFAsmParser.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/AsmParser/BPFAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/BPF/AsmParser/BPFAsmParser.cpp Thu Nov 1 12:54:45 2018
@@ -357,8 +357,8 @@ BPFAsmParser::parseOperandAsOperator(Ope
case AsmToken::Plus: {
if (getLexer().peekTok().is(AsmToken::Integer))
return MatchOperand_NoMatch;
+ LLVM_FALLTHROUGH;
}
- // Fall through.
case AsmToken::Equal:
case AsmToken::Greater:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp Thu Nov 1 12:54:45 2018
@@ -1208,6 +1208,7 @@ void HCE::recordExtender(MachineInstr &M
case Hexagon::S4_subaddi: // (__: ## - Rs<<0)
ED.Expr.Rs = MI.getOperand(OpNum+1);
ED.Expr.Neg = true;
+ break;
default: // (__: ## + __<<_)
break;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp Thu Nov 1 12:54:45 2018
@@ -2463,6 +2463,7 @@ APInt HexagonConstEvaluator::getCmpImm(u
case Hexagon::A4_cmpheqi: // s8
case Hexagon::C4_cmpneqi: // s8
Signed = true;
+ break;
case Hexagon::A4_cmpbeqi: // u8
break;
case Hexagon::C2_cmpgtui: // u9
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Thu Nov 1 12:54:45 2018
@@ -1547,6 +1547,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(c
return true;
}
}
+ break;
}
default:
break;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Thu Nov 1 12:54:45 2018
@@ -105,6 +105,7 @@ bool VLIWResourceModel::isResourceAvaila
default:
if (!ResourcesModel->canReserveResources(*SU->getInstr()))
return false;
+ break;
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Thu Nov 1 12:54:45 2018
@@ -1568,6 +1568,7 @@ bool HexagonPacketizerList::isLegalToPac
if (GlueAllocframeStore)
continue;
}
+ break;
default:
break;
}
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Nov 1 12:54:45 2018
@@ -767,13 +767,13 @@ public:
~MipsOperand() override {
switch (Kind) {
- case k_Immediate:
- break;
case k_Memory:
delete Mem.Base;
break;
case k_RegList:
delete RegList.List;
+ break;
+ case k_Immediate:
case k_RegisterIndex:
case k_Token:
break;
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Nov 1 12:54:45 2018
@@ -561,6 +561,7 @@ bool MipsAsmPrinter::PrintAsmOperand(con
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
}
+ break;
}
case 'w':
// Print MSA registers for the 'f' constraint
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Nov 1 12:54:45 2018
@@ -244,7 +244,7 @@ void MipsSEDAGToDAGISel::processFunction
MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
break;
}
- // fallthrough
+ LLVM_FALLTHROUGH;
case Mips::BuildPairF64:
case Mips::ExtractElementF64:
if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Thu Nov 1 12:54:45 2018
@@ -903,7 +903,7 @@ bool PPCFastISel::PPCEmitCmp(const Value
case MVT::i8:
case MVT::i16:
NeedsExt = true;
- // Intentional fall-through.
+ LLVM_FALLTHROUGH;
case MVT::i32:
if (!UseImm)
CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 1 12:54:45 2018
@@ -3970,7 +3970,7 @@ SDValue PPCTargetLowering::LowerFormalAr
assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
"Invalid QPX parameter type");
- /* fall through */
+ LLVM_FALLTHROUGH;
case MVT::v4f64:
case MVT::v4i1:
@@ -6113,7 +6113,7 @@ SDValue PPCTargetLowering::LowerCall_64S
assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
"Invalid QPX parameter type");
- /* fall through */
+ LLVM_FALLTHROUGH;
case MVT::v4f64:
case MVT::v4i1: {
bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Nov 1 12:54:45 2018
@@ -1308,7 +1308,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadSto
return false;
case SystemZISD::SSUBO:
NegateOperand = true;
- /* fall through */
+ LLVM_FALLTHROUGH;
case SystemZISD::SADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ASI;
@@ -1319,7 +1319,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadSto
break;
case SystemZISD::USUBO:
NegateOperand = true;
- /* fall through */
+ LLVM_FALLTHROUGH;
case SystemZISD::UADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ALSI;
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp Thu Nov 1 12:54:45 2018
@@ -447,6 +447,7 @@ unsigned WebAssemblyFastISel::zeroExtend
(isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr()))
return copyValue(Reg);
}
+ break;
case MVT::i8:
case MVT::i16:
break;
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=345882&r1=345881&r2=345882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu Nov 1 12:54:45 2018
@@ -1393,7 +1393,7 @@ static int readModRM(struct InternalInst
break;
case 0x1:
insn->displacementSize = 1;
- /* FALLTHROUGH */
+ LLVM_FALLTHROUGH;
case 0x2:
insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
switch (rm & 7) {
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