[llvm] r345634 - [AArch64] [Windows] SEH opcodes should be scheduling boundaries.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 30 12:24:51 PDT 2018
Author: efriedma
Date: Tue Oct 30 12:24:51 2018
New Revision: 345634
URL: http://llvm.org/viewvc/llvm-project?rev=345634&view=rev
Log:
[AArch64] [Windows] SEH opcodes should be scheduling boundaries.
Prevents the post-RA scheduler from modifying the prologue sequences
emitting by frame lowering. This is roughly similar to what we do for
other targets: TargetInstrInfo::isSchedulingBoundary checks
isPosition(), which checks for CFI_INSTRUCTION.
isSEHInstruction is taken from D50288; it'll land with whatever patch
lands first.
Differential Revision: https://reviews.llvm.org/D53851
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/test/CodeGen/AArch64/wineh1.mir
llvm/trunk/test/CodeGen/AArch64/wineh2.mir
llvm/trunk/test/CodeGen/AArch64/wineh3.mir
llvm/trunk/test/CodeGen/AArch64/wineh4.mir
llvm/trunk/test/CodeGen/AArch64/wineh5.mir
llvm/trunk/test/CodeGen/AArch64/wineh6.mir
llvm/trunk/test/CodeGen/AArch64/wineh7.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Oct 30 12:24:51 2018
@@ -1085,6 +1085,32 @@ bool AArch64InstrInfo::isFalkorShiftExtF
}
}
+bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
+ switch (Opc) {
+ default:
+ return false;
+ case AArch64::SEH_StackAlloc:
+ case AArch64::SEH_SaveFPLR:
+ case AArch64::SEH_SaveFPLR_X:
+ case AArch64::SEH_SaveReg:
+ case AArch64::SEH_SaveReg_X:
+ case AArch64::SEH_SaveRegP:
+ case AArch64::SEH_SaveRegP_X:
+ case AArch64::SEH_SaveFReg:
+ case AArch64::SEH_SaveFReg_X:
+ case AArch64::SEH_SaveFRegP:
+ case AArch64::SEH_SaveFRegP_X:
+ case AArch64::SEH_SetFP:
+ case AArch64::SEH_AddFP:
+ case AArch64::SEH_Nop:
+ case AArch64::SEH_PrologEnd:
+ case AArch64::SEH_EpilogStart:
+ case AArch64::SEH_EpilogEnd:
+ return true;
+ }
+}
+
bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SubIdx) const {
@@ -1137,6 +1163,14 @@ bool AArch64InstrInfo::areMemAccessesTri
return false;
}
+bool AArch64InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
+ const MachineBasicBlock *MBB,
+ const MachineFunction &MF) const {
+ if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF))
+ return true;
+ return isSEHInstruction(MI);
+}
+
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
/// Return true if the comparison instruction can be analyzed.
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Tue Oct 30 12:24:51 2018
@@ -189,6 +189,10 @@ public:
unsigned FalseReg) const override;
void getNoop(MCInst &NopInst) const override;
+ bool isSchedulingBoundary(const MachineInstr &MI,
+ const MachineBasicBlock *MBB,
+ const MachineFunction &MF) const override;
+
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
/// Return true if the comparison instruction can be analyzed.
@@ -262,6 +266,9 @@ public:
/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.
bool isFalkorShiftExtFast(const MachineInstr &MI) const;
+ /// Return true if the instructions is a SEH instruciton used for unwinding
+ /// on Windows.
+ static bool isSEHInstruction(const MachineInstr &MI);
private:
/// Sets the offsets on outlined instructions in \p MBB which use SP
Modified: llvm/trunk/test/CodeGen/AArch64/wineh1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh1.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh1.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh1.mir Tue Oct 30 12:24:51 2018
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj -disable-post-ra \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj \
# RUN: | llvm-readobj -unwind | FileCheck %s
# This test case checks the basic validity of the .xdata section. It's
# documented at:
Modified: llvm/trunk/test/CodeGen/AArch64/wineh2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh2.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh2.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh2.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Test that the pre/post increment save of a flating point register is correct.
# CHECK: ExceptionData {
Modified: llvm/trunk/test/CodeGen/AArch64/wineh3.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh3.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh3.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh3.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Test that the register pairing of both general purpose and floating point
# registers is correctly saved in the .xdata section, as well as the pre/post
# increment of floating point register pairs.
Modified: llvm/trunk/test/CodeGen/AArch64/wineh4.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh4.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh4.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh4.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -disable-branch-fold -disable-post-ra -filetype=obj \
+# RUN: -disable-branch-fold -filetype=obj \
# RUN: | llvm-readobj -unwind | FileCheck %s
# Check that multiple epilgoues are correctly placed in .xdata.
Modified: llvm/trunk/test/CodeGen/AArch64/wineh5.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh5.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh5.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh5.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check that that the large stack allocation is correctly represented in .xdata.
Modified: llvm/trunk/test/CodeGen/AArch64/wineh6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh6.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh6.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh6.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check save_fplr_x, set_fp, alloc_s
# CHECK: ExceptionData {
Modified: llvm/trunk/test/CodeGen/AArch64/wineh7.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/wineh7.mir?rev=345634&r1=345633&r2=345634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/wineh7.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/wineh7.mir Tue Oct 30 12:24:51 2018
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN: -filetype=obj -disable-post-ra | llvm-readobj -unwind | FileCheck %s
+# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check AddFP
# CHECK: ExceptionData {
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