[PATCH] D53784: [DAGCombiner] narrow vector binops when extraction is cheap

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/X86/avx2-schedule.ll:238
   %4 = shufflevector <8 x i32> %2, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   store <4 x i32> %3, <4 x i32> *%a2
   ret <4 x i32> %4
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This needs looking at - its supposed to test the schedule of the vextracti128 rr/mr ops  - the add/sub are purely there to keep the correct domain. If all else fails you can convert it to inline asm.


https://reviews.llvm.org/D53784