[PATCH] D53542: [WebAssembly] Set LoadExt and TruncStore actions for SIMD types

[Thomas Lively via Phabricator via llvm-commits]

tlively added inline comments.


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Comment at: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:186
+                   MVT::v2f64})
+      for (auto MemT : MVT::vector_valuetypes())
+        if (MVT(T) != MemT) {
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aheejin wrote:
> - What happens if `T` and `MVT` have different number of elements? (v16i8 vs. v64i2)
> - What happens if they have the same number of elements but the size of vectors are different? (v16i8 vs. v16i16)
> - What if both of these are true? (v16i8 vs. v64i16)
I believe nothing changes if `T` and `MVT` have different numbers of elements. It should not be possible for a DAG to get into that state. Writing the code this way is just shorter than finding the minimum set of actions that need to be set.

The extending loads and truncating stores are for exactly the case when the in-memory vector has smaller lane sizes than the in-register vector. This code expands those cases to load or store the vectors one lane at a time. I believe it is not possible to have in-memory lanes that are larger than the in-register lanes.


Repository:
  rL LLVM

https://reviews.llvm.org/D53542