[llvm] r345187 - [AArch64] Refactor Exynos machine model (NFC)
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 24 13:03:24 PDT 2018
Author: evandro
Date: Wed Oct 24 13:03:24 2018
New Revision: 345187
URL: http://llvm.org/viewvc/llvm-project?rev=345187&view=rev
Log:
[AArch64] Refactor Exynos machine model (NFC)
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td
llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=345187&r1=345186&r2=345187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed Oct 24 13:03:24 2018
@@ -696,7 +696,7 @@ bool AArch64InstrInfo::isAsCheapAsAMove(
// Secondly, check cases specific to sub-targets.
if (Subtarget.hasExynosCheapAsMoveHandling()) {
- if (isExynosResetFast(MI) || isExynosShiftLeftFast(MI))
+ if (isExynosResetFast(MI) || isExynosShiftExtFast(MI))
return true;
else
return MI.isAsCheapAsAMove();
@@ -821,7 +821,7 @@ bool AArch64InstrInfo::isExynosResetFast
}
}
-bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isExynosShiftExtFast(const MachineInstr &MI) const {
unsigned Imm, Shift;
AArch64_AM::ShiftExtendType Ext;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=345187&r1=345186&r2=345187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Wed Oct 24 13:03:24 2018
@@ -255,7 +255,7 @@ public:
bool isExynosResetFast(const MachineInstr &MI) const;
/// Returns true if the instruction has a shift left that can be executed
/// more efficiently.
- bool isExynosShiftLeftFast(const MachineInstr &MI) const;
+ bool isExynosShiftExtFast(const MachineInstr &MI) const;
/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.
bool isFalkorShiftExtFast(const MachineInstr &MI) const;
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td?rev=345187&r1=345186&r2=345187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td Wed Oct 24 13:03:24 2018
@@ -64,9 +64,9 @@ def M1UnitNALU : ProcResGroup<[M1UnitNAL
//===----------------------------------------------------------------------===//
// Predicates.
-def M1BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
- MI->getOperand(0).getReg() != AArch64::LR}]>;
-def M1ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
+def M1BranchLinkPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
+ MI->getOperand(0).getReg() != AArch64::LR}]>;
+def M1ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
//===----------------------------------------------------------------------===//
// Coarse scheduling model.
@@ -85,14 +85,14 @@ def M1WriteAC : SchedWriteRes<[M1UnitALU
def M1WriteAD : SchedWriteRes<[M1UnitALU,
M1UnitC]> { let Latency = 2;
let NumMicroOps = 2; }
-def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteA1]>,
- SchedVar<NoSchedPred, [M1WriteAA]>]>;
+def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteA1]>,
+ SchedVar<NoSchedPred, [M1WriteAA]>]>;
def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
-def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteAB]>,
- SchedVar<NoSchedPred, [M1WriteAC]>]>;
+def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkPred, [M1WriteAB]>,
+ SchedVar<NoSchedPred, [M1WriteAC]>]>;
def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
@@ -110,10 +110,10 @@ def M1WriteLD : SchedWriteRes<[M1UnitL,
let ResourceCycles = [2, 1]; }
def M1WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
-def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
- SchedVar<NoSchedPred, [M1WriteLC]>]>;
-def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
- SchedVar<NoSchedPred, [M1WriteLD]>]>;
+def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
+ SchedVar<NoSchedPred, [M1WriteLC]>]>;
+def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
+ SchedVar<NoSchedPred, [M1WriteLD]>]>;
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
def M1WriteS3 : SchedWriteRes<[M1UnitS]> { let Latency = 3; }
@@ -140,10 +140,10 @@ def M1WriteSD : SchedWriteRes<[M1UnitS,
def M1WriteSE : SchedWriteRes<[M1UnitS,
M1UnitA]> { let Latency = 2;
let NumMicroOps = 2; }
-def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
- SchedVar<NoSchedPred, [M1WriteSE]>]>;
-def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
- SchedVar<NoSchedPred, [M1WriteSB]>]>;
+def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
+ SchedVar<NoSchedPred, [M1WriteSE]>]>;
+def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
+ SchedVar<NoSchedPred, [M1WriteSB]>]>;
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=345187&r1=345186&r2=345187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Wed Oct 24 13:03:24 2018
@@ -106,15 +106,15 @@ def M3UnitNSHF : ProcResGroup<[M3UnitNSH
//===----------------------------------------------------------------------===//
// Predicates.
-def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
- MI->getOperand(0).isReg() &&
- MI->getOperand(0).getReg() != AArch64::LR}]>;
-def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
-def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
- MI->getOpcode() == AArch64::EXTRXrri) &&
- MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
- MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
-def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
+def M3BranchLinkPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
+ MI->getOperand(0).isReg() &&
+ MI->getOperand(0).getReg() != AArch64::LR}]>;
+def M3ResetPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
+def M3RotatePred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
+ MI->getOpcode() == AArch64::EXTRXrri) &&
+ MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
+def M3ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
//===----------------------------------------------------------------------===//
// Coarse scheduling model.
@@ -137,15 +137,15 @@ def M3WriteAD : SchedWriteRes<[M3UnitALU
let NumMicroOps = 2; }
def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
-def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>,
- SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
- SchedVar<NoSchedPred, [M3WriteAA]>]>;
-def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>,
- SchedVar<NoSchedPred, [M3WriteAA]>]>;
+def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetPred, [M3WriteZ0]>,
+ SchedVar<M3ShiftExtPred, [M3WriteA1]>,
+ SchedVar<NoSchedPred, [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotatePred, [M3WriteA1]>,
+ SchedVar<NoSchedPred, [M3WriteAA]>]>;
def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
-def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
- SchedVar<NoSchedPred, [M3WriteAC]>]>;
+def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkPred, [M3WriteAB]>,
+ SchedVar<NoSchedPred, [M3WriteAC]>]>;
def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
@@ -165,8 +165,8 @@ def M3WriteLD : SchedWriteRes<[M3UnitA,
def M3WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
-def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteL5]>,
- SchedVar<NoSchedPred, [M3WriteLB]>]>;
+def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteL5]>,
+ SchedVar<NoSchedPred, [M3WriteLB]>]>;
def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; }
def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -180,10 +180,10 @@ def M3WriteSC : SchedWriteRes<[M3UnitA,
M3UnitS]> { let Latency = 2;
let NumMicroOps = 2; }
-def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>,
- SchedVar<NoSchedPred, [M3WriteSB]>]>;
-def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>,
- SchedVar<NoSchedPred, [M3WriteSC]>]>;
+def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
+ SchedVar<NoSchedPred, [M3WriteSB]>]>;
+def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
+ SchedVar<NoSchedPred, [M3WriteSC]>]>;
def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
@@ -481,8 +481,8 @@ def M3WriteAES : SchedWriteRes<[M3Un
def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>;
def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4,
M3WriteFMAC5]>;
-def M3WriteMOVI : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>,
- SchedVar<NoSchedPred, [M3WriteNALU1]>]>;
+def M3WriteMOVI : SchedWriteVariant<[SchedVar<M3ResetPred, [M3WriteZ0]>,
+ SchedVar<NoSchedPred, [M3WriteNALU1]>]>;
def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>;
// Branch instructions
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