[llvm] r344826 - [WebAssembly] Implement vector sext_inreg and tests with comparisons
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 19 18:35:23 PDT 2018
Author: tlively
Date: Fri Oct 19 18:35:23 2018
New Revision: 344826
URL: http://llvm.org/viewvc/llvm-project?rev=344826&view=rev
Log:
[WebAssembly] Implement vector sext_inreg and tests with comparisons
Summary: Depends on D53251.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53252
Added:
llvm/trunk/test/CodeGen/WebAssembly/simd-sext-inreg.ll
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/CodeGen/WebAssembly/simd-comparisons.ll
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=344826&r1=344825&r2=344826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Fri Oct 19 18:35:23 2018
@@ -48,6 +48,8 @@ WebAssemblyTargetLowering::WebAssemblyTa
// Booleans always contain 0 or 1.
setBooleanContents(ZeroOrOneBooleanContent);
+ // Except in SIMD vectors
+ setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
// WebAssembly does not produce floating-point exceptions on normal floating
// point operations.
setHasFloatingPointExceptions(false);
@@ -149,6 +151,8 @@ WebAssemblyTargetLowering::WebAssemblyTa
for (auto T : {MVT::i8, MVT::i16, MVT::i32})
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
}
+ for (auto T : MVT::integer_vector_valuetypes())
+ setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
// Dynamic stack allocation: use the default expansion.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=344826&r1=344825&r2=344826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Fri Oct 19 18:35:23 2018
@@ -613,7 +613,8 @@ multiclass SIMDCondition<ValueType vec_t
defm _#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
[(set (out_t V128:$dst),
- (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond))],
+ (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
+ )],
vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
}
@@ -621,15 +622,15 @@ multiclass SIMDConditionInt<string name,
int step = 1> {
defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
- !add(baseInst, step)>;
+ !add(baseInst, step)>;
defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
- !add(!add(baseInst, step), step)>;
+ !add(!add(baseInst, step), step)>;
}
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
- !add(baseInst, 1)>;
+ !add(baseInst, 1)>;
}
// Equality: eq
Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-comparisons.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-comparisons.ll?rev=344826&r1=344825&r2=344826&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-comparisons.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-comparisons.ll Fri Oct 19 18:35:23 2018
@@ -1,6 +1,6 @@
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; Test SIMD comparison operators
@@ -18,6 +18,18 @@ define <16 x i1> @compare_eq_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_eq_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_eq_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp eq <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_ne_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -29,6 +41,18 @@ define <16 x i1> @compare_ne_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_ne_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_ne_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp ne <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_slt_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -40,6 +64,18 @@ define <16 x i1> @compare_slt_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_slt_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_slt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp slt <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_ult_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -51,6 +87,18 @@ define <16 x i1> @compare_ult_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_ult_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_ult_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp ult <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_sle_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -62,6 +110,18 @@ define <16 x i1> @compare_sle_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_sle_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_sle_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp sle <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_ule_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -73,6 +133,18 @@ define <16 x i1> @compare_ule_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_ule_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_ule_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp ule <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_sgt_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -84,6 +156,18 @@ define <16 x i1> @compare_sgt_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_sgt_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_sgt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp sgt <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_ugt_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -95,6 +179,18 @@ define <16 x i1> @compare_ugt_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_ugt_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_ugt_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp ugt <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_sge_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -106,6 +202,18 @@ define <16 x i1> @compare_sge_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_sge_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_sge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp sge <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_uge_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -117,6 +225,18 @@ define <16 x i1> @compare_uge_v16i8 (<16
ret <16 x i1> %res
}
+; CHECK-LABEL: compare_sext_uge_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @compare_sext_uge_v16i8 (<16 x i8> %x, <16 x i8> %y) {
+ %cmp = icmp uge <16 x i8> %x, %y
+ %res = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %res
+}
+
; CHECK-LABEL: compare_eq_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -128,6 +248,18 @@ define <8 x i1> @compare_eq_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_eq_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_eq_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp eq <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_ne_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -139,6 +271,18 @@ define <8 x i1> @compare_ne_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_ne_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_ne_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp ne <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_slt_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -150,6 +294,18 @@ define <8 x i1> @compare_slt_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_slt_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_slt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp slt <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_ult_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -161,6 +317,18 @@ define <8 x i1> @compare_ult_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_ult_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_ult_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp ult <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_sle_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -172,6 +340,18 @@ define <8 x i1> @compare_sle_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_sle_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_sle_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp sle <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_ule_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -183,6 +363,18 @@ define <8 x i1> @compare_ule_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_ule_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_ule_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp ule <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_sgt_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -194,6 +386,18 @@ define <8 x i1> @compare_sgt_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_sgt_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_sgt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp sgt <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_ugt_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -205,6 +409,18 @@ define <8 x i1> @compare_ugt_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_ugt_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_ugt_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp ugt <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_sge_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -216,6 +432,18 @@ define <8 x i1> @compare_sge_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_sge_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_sge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp sge <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_uge_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -227,6 +455,18 @@ define <8 x i1> @compare_uge_v8i16 (<8 x
ret <8 x i1> %res
}
+; CHECK-LABEL: compare_sext_uge_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @compare_sext_uge_v8i16 (<8 x i16> %x, <8 x i16> %y) {
+ %cmp = icmp uge <8 x i16> %x, %y
+ %res = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %res
+}
+
; CHECK-LABEL: compare_eq_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -238,6 +478,18 @@ define <4 x i1> @compare_eq_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_eq_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_eq_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp eq <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ne_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -249,6 +501,18 @@ define <4 x i1> @compare_ne_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ne_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ne_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp ne <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_slt_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -260,6 +524,18 @@ define <4 x i1> @compare_slt_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_slt_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_slt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp slt <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ult_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -271,6 +547,18 @@ define <4 x i1> @compare_ult_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ult_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.lt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ult_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp ult <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_sle_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -282,6 +570,18 @@ define <4 x i1> @compare_sle_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_sle_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_sle_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp sle <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ule_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -293,6 +593,18 @@ define <4 x i1> @compare_ule_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ule_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.le_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ule_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp ule <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_sgt_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -304,6 +616,18 @@ define <4 x i1> @compare_sgt_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_sgt_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_sgt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp sgt <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ugt_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -315,6 +639,18 @@ define <4 x i1> @compare_ugt_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ugt_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.gt_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ugt_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp ugt <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_sge_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -326,6 +662,18 @@ define <4 x i1> @compare_sge_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_sge_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_sge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp sge <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_uge_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -337,6 +685,18 @@ define <4 x i1> @compare_uge_v4i32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_uge_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.ge_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
+ %cmp = icmp uge <4 x i32> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_oeq_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -348,6 +708,18 @@ define <4 x i1> @compare_oeq_v4f32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_oeq_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_oeq_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp oeq <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ogt_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -359,6 +731,18 @@ define <4 x i1> @compare_ogt_v4f32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ogt_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ogt_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ogt <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_oge_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -370,6 +754,18 @@ define <4 x i1> @compare_oge_v4f32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_oge_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_oge_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp oge <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_olt_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -381,6 +777,18 @@ define <4 x i1> @compare_olt_v4f32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_olt_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_olt_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp olt <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ole_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -392,97 +800,257 @@ define <4 x i1> @compare_ole_v4f32 (<4 x
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ole_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.le $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ole_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ole <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_one_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.ne
+; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_one_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp one <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_one_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_one_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp one <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ord_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.eq
+; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ord <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ord_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ord <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ueq_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.eq
+; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ueq <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ueq_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x i32> @compare_sext_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ueq <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ugt_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.le
+; SIMD128-NEXT: f32x4.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ugt_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ugt <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ugt_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ugt_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ugt <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_uge_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.lt
+; SIMD128-NEXT: f32x4.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_uge_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp uge <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_uge_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_uge_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp uge <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ult_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.ge
+; SIMD128-NEXT: f32x4.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ult_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ult <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ult_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ult_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ult <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_ule_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.gt
+; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ule_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ule <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_ule_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_ule_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp ule <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_une_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_une_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp une <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_une_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_une_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp une <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_uno_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f32x4.ne
+; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp uno <4 x float> %x, %y
ret <4 x i1> %res
}
+; CHECK-LABEL: compare_sext_uno_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @compare_sext_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
+ %cmp = fcmp uno <4 x float> %x, %y
+ %res = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %res
+}
+
; CHECK-LABEL: compare_oeq_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -495,6 +1063,19 @@ define <2 x i1> @compare_oeq_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_oeq_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_oeq_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp oeq <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ogt_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -507,6 +1088,19 @@ define <2 x i1> @compare_ogt_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ogt_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ogt_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ogt <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_oge_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -519,6 +1113,19 @@ define <2 x i1> @compare_oge_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_oge_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_oge_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp oge <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_olt_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -531,6 +1138,19 @@ define <2 x i1> @compare_olt_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_olt_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_olt_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp olt <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ole_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -543,83 +1163,222 @@ define <2 x i1> @compare_ole_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ole_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ole_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ole <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_one_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.ne
+; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_one_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp one <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_one_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_one_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp one <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ord_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.eq
+; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ord <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ord_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ord <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ueq_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.eq
+; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ueq <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ueq_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ueq <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ugt_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.le
+; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ugt <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ugt_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ugt <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_uge_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.lt
+; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp uge <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_uge_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp uge <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ult_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.ge
+; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ult <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ult_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ult <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_ule_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.gt
+; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ule <2 x double> %x, %y
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_ule_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp ule <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_une_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
@@ -632,13 +1391,44 @@ define <2 x i1> @compare_une_v2f64 (<2 x
ret <2 x i1> %res
}
+; CHECK-LABEL: compare_sext_une_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_une_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp une <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
+
; CHECK-LABEL: compare_uno_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f64x2
; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
-; SIMD128-NEXT: f64x2.ne
+; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp uno <2 x double> %x, %y
ret <2 x i1> %res
}
+
+; CHECK-LABEL: compare_sext_uno_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
+; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
+; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @compare_sext_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
+ %cmp = fcmp uno <2 x double> %x, %y
+ %res = sext <2 x i1> %cmp to <2 x i64>
+ ret <2 x i64> %res
+}
Added: llvm/trunk/test/CodeGen/WebAssembly/simd-sext-inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-sext-inreg.ll?rev=344826&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-sext-inreg.ll (added)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-sext-inreg.ll Fri Oct 19 18:35:23 2018
@@ -0,0 +1,65 @@
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
+; Test that vector sign extensions lower to shifts
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: sext_inreg_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
+; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
+; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
+; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @sext_inreg_v16i8(<16 x i1> %x) {
+ %res = sext <16 x i1> %x to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: sext_inreg_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
+; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
+; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
+; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @sext_inreg_v8i16(<8 x i1> %x) {
+ %res = sext <8 x i1> %x to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: sext_inreg_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
+; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
+; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
+; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @sext_inreg_v4i32(<4 x i1> %x) {
+ %res = sext <4 x i1> %x to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: sext_inreg_v2i64:
+; NO-SIMD128-NOT: i64x2
+; SDIM128-VM-NOT: i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
+; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
+; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
+; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @sext_inreg_v2i64(<2 x i1> %x) {
+ %res = sext <2 x i1> %x to <2 x i64>
+ ret <2 x i64> %res
+}
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