[llvm] r344563 - [X86] Fix a bad bitcast in the load form of vXi16 uniform shift patterns for EVEX encoded instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 15 14:51:32 PDT 2018
Author: ctopper
Date: Mon Oct 15 14:51:32 2018
New Revision: 344563
URL: http://llvm.org/viewvc/llvm-project?rev=344563&view=rev
Log:
[X86] Fix a bad bitcast in the load form of vXi16 uniform shift patterns for EVEX encoded instructions.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=344563&r1=344562&r2=344563&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Oct 15 14:51:32 2018
@@ -5826,7 +5826,7 @@ multiclass avx512_shift_rmbi<bits<8> opc
multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
X86FoldableSchedWrite sched, ValueType SrcVT,
- PatFrag bc_frag, X86VectorVTInfo _> {
+ X86VectorVTInfo _> {
// src2 is always 128-bit
let ExeDomain = _.ExeDomain in {
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -5837,7 +5837,8 @@ multiclass avx512_shift_rrm<bits<8> opc,
defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src1, i128mem:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
- (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2))))>,
+ (_.VT (OpNode _.RC:$src1,
+ (SrcVT (bitconvert (loadv2i64 addr:$src2)))))>,
AVX512BIBase,
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
}
@@ -5845,18 +5846,18 @@ multiclass avx512_shift_rrm<bits<8> opc,
multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
X86SchedWriteWidths sched, ValueType SrcVT,
- PatFrag bc_frag, AVX512VLVectorVTInfo VTInfo,
+ AVX512VLVectorVTInfo VTInfo,
Predicate prd> {
let Predicates = [prd] in
defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, sched.ZMM, SrcVT,
- bc_frag, VTInfo.info512>, EVEX_V512,
+ VTInfo.info512>, EVEX_V512,
EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
let Predicates = [prd, HasVLX] in {
defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, sched.YMM, SrcVT,
- bc_frag, VTInfo.info256>, EVEX_V256,
+ VTInfo.info256>, EVEX_V256,
EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, sched.XMM, SrcVT,
- bc_frag, VTInfo.info128>, EVEX_V128,
+ VTInfo.info128>, EVEX_V128,
EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
}
}
@@ -5866,12 +5867,12 @@ multiclass avx512_shift_types<bits<8> op
X86SchedWriteWidths sched,
bit NotEVEX2VEXConvertibleQ = 0> {
defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, sched, v4i32,
- bc_v4i32, avx512vl_i32_info, HasAVX512>;
+ avx512vl_i32_info, HasAVX512>;
let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in
defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, sched, v2i64,
- bc_v2i64, avx512vl_i64_info, HasAVX512>, VEX_W;
+ avx512vl_i64_info, HasAVX512>, VEX_W;
defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, sched, v8i16,
- bc_v2i64, avx512vl_i16_info, HasBWI>;
+ avx512vl_i16_info, HasBWI>;
}
multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=344563&r1=344562&r2=344563&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Mon Oct 15 14:51:32 2018
@@ -541,8 +541,7 @@ define <16 x i16> @test_x86_avx2_psrl_w_
; X86-AVX512VL-LABEL: test_x86_avx2_psrl_w_load:
; X86-AVX512VL: ## %bb.0:
; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; X86-AVX512VL-NEXT: vmovdqa (%eax), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x08]
-; X86-AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
+; X86-AVX512VL-NEXT: vpsrlw (%eax), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0x00]
; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrl_w_load:
@@ -552,8 +551,7 @@ define <16 x i16> @test_x86_avx2_psrl_w_
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrl_w_load:
; X64-AVX512VL: ## %bb.0:
-; X64-AVX512VL-NEXT: vmovdqa (%rdi), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x0f]
-; X64-AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
+; X64-AVX512VL-NEXT: vpsrlw (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0x07]
; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%a1 = load <8 x i16>, <8 x i16>* %p
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=344563&r1=344562&r2=344563&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Mon Oct 15 14:51:32 2018
@@ -1952,14 +1952,12 @@ define <32 x i16> @test_x86_avx512_psrl_
; X86-LABEL: test_x86_avx512_psrl_w_512_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
-; X86-NEXT: vmovdqa (%eax), %xmm1 # encoding: [0xc5,0xf9,0x6f,0x08]
-; X86-NEXT: vpsrlw %xmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xd1,0xc1]
+; X86-NEXT: vpsrlw (%eax), %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xd1,0x00]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_x86_avx512_psrl_w_512_load:
; X64: # %bb.0:
-; X64-NEXT: vmovdqa (%rdi), %xmm1 # encoding: [0xc5,0xf9,0x6f,0x0f]
-; X64-NEXT: vpsrlw %xmm1, %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xd1,0xc1]
+; X64-NEXT: vpsrlw (%rdi), %zmm0, %zmm0 # encoding: [0x62,0xf1,0x7d,0x48,0xd1,0x07]
; X64-NEXT: retq # encoding: [0xc3]
%a1 = load <8 x i16>, <8 x i16>* %p
%res = call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %a0, <8 x i16> %a1) ; <<32 x i16>> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=344563&r1=344562&r2=344563&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Mon Oct 15 14:51:32 2018
@@ -1434,8 +1434,7 @@ define <8 x i16> @test_x86_sse2_psrl_w_l
; X86-AVX512-LABEL: test_x86_sse2_psrl_w_load:
; X86-AVX512: ## %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; X86-AVX512-NEXT: vmovdqa (%eax), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x08]
-; X86-AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0xc1]
+; X86-AVX512-NEXT: vpsrlw (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0x00]
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse2_psrl_w_load:
@@ -1450,8 +1449,7 @@ define <8 x i16> @test_x86_sse2_psrl_w_l
;
; X64-AVX512-LABEL: test_x86_sse2_psrl_w_load:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovdqa (%rdi), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x0f]
-; X64-AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0xc1]
+; X64-AVX512-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0x07]
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%a1 = load <8 x i16>, <8 x i16>* %p
%res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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