[llvm] r344466 - [AARCH64] Regenerate popcnt tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 13 14:50:15 PDT 2018
Author: rksimon
Date: Sat Oct 13 14:50:15 2018
New Revision: 344466
URL: http://llvm.org/viewvc/llvm-project?rev=344466&view=rev
Log:
[AARCH64] Regenerate popcnt tests
Improve codegen view as part of PR32655
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll?rev=344466&r1=344465&r2=344466&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll Sat Oct 13 14:50:15 2018
@@ -1,65 +1,190 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-apple- -mcpu=cyclone | FileCheck %s
; The non-byte ones used to fail with "Cannot select"
-; CHECK-LABEL: ctpopv8i8
-; CHECK: cnt.8b
define <8 x i8> @ctpopv8i8(<8 x i8> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: ret
%cnt = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %x)
ret <8 x i8> %cnt
}
declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
-; CHECK-LABEL: ctpopv4i16
-; CHECK: cnt.8b
define <4 x i16> @ctpopv4i16(<4 x i16> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: umov w8, v0.h[0]
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: umov w8, v0.h[1]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[1], w8
+; CHECK-NEXT: umov w8, v0.h[2]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[2], w8
+; CHECK-NEXT: umov w8, v0.h[3]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov v1.h[3], w8
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%cnt = tail call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %x)
ret <4 x i16> %cnt
}
declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
-; CHECK-LABEL: ctpopv2i32
-; CHECK: cnt.8b
define <2 x i32> @ctpopv2i32(<2 x i32> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov w8, v0.s[1]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%cnt = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %x)
ret <2 x i32> %cnt
}
declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
-
-; CHECK-LABEL: ctpopv16i8
-; CHECK: cnt.16b
define <16 x i8> @ctpopv16i8(<16 x i8> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v0.16b, v0.16b
+; CHECK-NEXT: ret
%cnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)
ret <16 x i8> %cnt
}
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
-; CHECK-LABEL: ctpopv8i16
-; CHECK: cnt.8b
define <8 x i16> @ctpopv8i16(<8 x i16> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umov w8, v0.h[1]
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: umov w9, v0.h[0]
+; CHECK-NEXT: fmov d1, x9
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: mov v1.h[1], w8
+; CHECK-NEXT: umov w8, v0.h[2]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[2], w8
+; CHECK-NEXT: umov w8, v0.h[3]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[3], w8
+; CHECK-NEXT: umov w8, v0.h[4]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[4], w8
+; CHECK-NEXT: umov w8, v0.h[5]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[5], w8
+; CHECK-NEXT: umov w8, v0.h[6]
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: cnt v2.8b, v2.8b
+; CHECK-NEXT: uaddlv h2, v2.8b
+; CHECK-NEXT: fmov w8, s2
+; CHECK-NEXT: mov v1.h[6], w8
+; CHECK-NEXT: umov w8, v0.h[7]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov v1.h[7], w8
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%cnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %x)
ret <8 x i16> %cnt
}
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
-; CHECK-LABEL: ctpopv4i32
-; CHECK: cnt.8b
define <4 x i32> @ctpopv4i32(<4 x i32> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, v0.s[1]
+; CHECK-NEXT: mov w9, v0.s[2]
+; CHECK-NEXT: mov w10, v0.s[3]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: fmov d1, x9
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[2], w8
+; CHECK-NEXT: fmov d1, x10
+; CHECK-NEXT: cnt v1.8b, v1.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: ret
%cnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x)
ret <4 x i32> %cnt
}
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
-; CHECK-LABEL: ctpopv2i64
-; CHECK: cnt.8b
define <2 x i64> @ctpopv2i64(<2 x i64> %x) nounwind readnone {
+; CHECK-LABEL: ctpopv2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cnt v1.8b, v0.8b
+; CHECK-NEXT: uaddlv h1, v1.8b
+; CHECK-NEXT: fmov w0, s1
+; CHECK-NEXT: fmov d1, x0
+; CHECK-NEXT: mov x8, v0.d[1]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: cnt v0.8b, v0.8b
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov v1.d[1], x8
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%cnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
ret <2 x i64> %cnt
}
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