[llvm] r344450 - Pull out repeated getOperand(). NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Oct 13 06:33:32 2018
New Revision: 344450

URL: http://llvm.org/viewvc/llvm-project?rev=344450&view=rev
Log:
Pull out repeated getOperand(). NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=344450&r1=344449&r2=344450&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Oct 13 06:33:32 2018
@@ -22972,11 +22972,10 @@ static SDValue LowerCTTZ(SDValue Op, con
                          SelectionDAG &DAG) {
   MVT VT = Op.getSimpleValueType();
   unsigned NumBits = VT.getScalarSizeInBits();
+  SDValue N0 = Op.getOperand(0);
   SDLoc dl(Op);
 
   if (VT.isVector()) {
-    SDValue N0 = Op.getOperand(0);
-
     // Decompose 256-bit ops into smaller 128-bit ops.
     if (VT.is256BitVector() && !Subtarget.hasInt256())
       return Lower256IntUnary(Op, DAG);
@@ -23004,7 +23003,7 @@ static SDValue LowerCTTZ(SDValue Op, con
 
   // Issue a bsf (scan bits forward) which also sets EFLAGS.
   SDVTList VTs = DAG.getVTList(VT, MVT::i32);
-  Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
+  Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0);
 
   // If src is zero (i.e. bsf sets ZF), returns NumBits.
   SDValue Ops[] = {