[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: apazos, sabuasal, eli.friedman, bogner.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, simoncook, johnrusso, rbar.

This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32
to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+sext for f32->i64 and trunc+bitcast for i64->f32. Custom-lower ISD::BITCAST to select these nodes during legalisation. This makes it necessary to introduce a trivial fold for anyext where FromTy and ToTy are identical.


https://reviews.llvm.org/D53235

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-br-fcmp.ll
  test/CodeGen/RISCV/float-convert.ll
  test/CodeGen/RISCV/float-fcmp.ll
  test/CodeGen/RISCV/float-imm.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/float-select-fcmp.ll

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