[PATCH] D53057: [WebAssembly] Handle undefined lane indices in SIMD patterns

[Heejin Ahn via Phabricator via llvm-commits]

aheejin added inline comments.


================
Comment at: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1032
+      // Lower undefs to zero
+      uint64_t MaskVal = Mask[I] == -1 ? 0 : (uint64_t)Mask[I] * LaneBytes + J;
+      Ops[OpIdx++] = DAG.getConstant(MaskVal, DL, MVT::i32);
----------------
Why -1? Is it how `undef` is represented?


================
Comment at: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:194
+def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
+          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
+def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
----------------
Are these unnecessary sequence of masking by `and` also removed in non-undef cases?


================
Comment at: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:202
+def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
+          (EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
+def : Pat<(vector_extract (v4i32 V128:$vec), undef),
----------------
Here the same. Are these `sext_inreg` also removed in non-undef cases?


================
Comment at: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:232
+def : Pat<(vector_extract (v2f64 V128:$vec), undef),
+          (EXTRACT_LANE_v2f64 V128:$vec, 0)>;
+def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
----------------
Move this pattern to extract_lane category above


================
Comment at: test/CodeGen/WebAssembly/simd.ll:133
+define <16 x i8> @replace_undef_v16i8(<16 x i8> %v, i8 %x) {
+  %res = insertelement <16 x i8> %v, i8 %x, i32 0
+  ret <16 x i8> %res
----------------
`i32 undef`? For all other `replace_undef_` functions too.


Repository:
  rL LLVM

https://reviews.llvm.org/D53057