[PATCH] D53190: ARM: avoid infinite combining loop

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: chrib, hiraditya, kristof.beyls, mcrosier.
Herald added a reviewer: javed.absar.

One of the transformations done by `PerformCMOVCombine` increases DAG complexity so that one of the output values can be shared with the compare operation (written as a `SUBS`). Since this is the reverse of normal combining, it can be collapsed back later in the worklist, leading to an infinite loop.

I think there was a little existing logic to avoid this (the `LHS != RHS` check) , but it's fragile and nowhere near covers all possible combines; I could not extend it satisfactorily to cover this case and others.

So this patch changes the inserted `ISD::SUB` into a new `ARMISD::OpaqueSUB` with the same semantics but that doesn't undergo combining to avoid the problem.


Repository:
  rL LLVM

https://reviews.llvm.org/D53190

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/CodeGen/ARM/select.ll

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