[PATCH] D53176: AArch64/TargetTransformInfo: Report div/rem constant immediate costs as TCC_Free

[Matthias Braun via Phabricator via llvm-commits]

MatzeB created this revision.
MatzeB added a reviewer: t.p.northover.
Herald added subscribers: kristof.beyls, mcrosier.
Herald added a reviewer: javed.absar.

DIV/REM instructions with constant operands are replaced by a series of
muls/shifts/etc. with different constants. Unfortunately the
ConstantHoisting pass runs too early to catch this expansion and will
operate on immediate that will get changed later. Report these
operations as TCC_Free so ConstantHoisting will not touch them.


Repository:
  rL LLVM

https://reviews.llvm.org/D53176

Files:
  lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  test/Transforms/ConstantHoisting/AArch64/bad-cases.ll


Index: test/Transforms/ConstantHoisting/AArch64/bad-cases.ll
===================================================================
--- /dev/null
+++ test/Transforms/ConstantHoisting/AArch64/bad-cases.ll
@@ -0,0 +1,47 @@
+; RUN: opt -consthoist -S < %s | FileCheck %s
+target triple = "aarch64--"
+
+; We don't want to convert constant divides because the benefit from converting
+; them to a mul in the backend is larget than constant materialization savings.
+define void @signed_const_division(i32 %in1, i32 %in2, i32* %addr) {
+; CHECK-LABEL: @signed_const_division
+; CHECK: %res1 = sdiv i32 %l1, 1000000000
+; CHECK: %res2 = srem i32 %l2, 1000000000
+entry:
+  br label %loop
+
+loop:
+  %l1 = phi i32 [%res1, %loop], [%in1, %entry]
+  %l2 = phi i32 [%res2, %loop], [%in2, %entry]
+  %res1 = sdiv i32 %l1, 1000000000
+  store volatile i32 %res1, i32* %addr
+  %res2 = srem i32 %l2, 1000000000
+  store volatile i32 %res2, i32* %addr
+  %again = icmp eq i32 %res1, %res2
+  br i1 %again, label %loop, label %end
+
+end:
+  ret void
+}
+
+define void @unsigned_const_division(i32 %in1, i32 %in2, i32* %addr) {
+; CHECK-LABEL: @unsigned_const_division
+; CHECK: %res1 = udiv i32 %l1, 1000000000
+; CHECK: %res2 = urem i32 %l2, 1000000000
+
+entry:
+  br label %loop
+
+loop:
+  %l1 = phi i32 [%res1, %loop], [%in1, %entry]
+  %l2 = phi i32 [%res2, %loop], [%in2, %entry]
+  %res1 = udiv i32 %l1, 1000000000
+  store volatile i32 %res1, i32* %addr
+  %res2 = urem i32 %l2, 1000000000
+  store volatile i32 %res2, i32* %addr
+  %again = icmp eq i32 %res1, %res2
+  br i1 %again, label %loop, label %end
+
+end:
+  ret void
+}
Index: lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -101,13 +101,17 @@
   case Instruction::Store:
     ImmIdx = 0;
     break;
-  case Instruction::Add:
-  case Instruction::Sub:
-  case Instruction::Mul:
   case Instruction::UDiv:
   case Instruction::SDiv:
   case Instruction::URem:
   case Instruction::SRem:
+    // Division by constant is typically expanded later into a different
+    // instruction sequence. This completely changes the constants.
+    // Report them as "free" to stop ConstantHoist from marking them as opaque.
+    return TTI::TCC_Free;
+  case Instruction::Add:
+  case Instruction::Sub:
+  case Instruction::Mul:
   case Instruction::And:
   case Instruction::Or:
   case Instruction::Xor:


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