[llvm] r344235 - [tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero physical registers.
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 11 03:39:03 PDT 2018
Author: adibiagio
Date: Thu Oct 11 03:39:03 2018
New Revision: 344235
URL: http://llvm.org/viewvc/llvm-project?rev=344235&view=rev
Log:
[tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero physical registers.
Modified:
llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
Modified: llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp?rev=344235&r1=344234&r2=344235&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp Thu Oct 11 03:39:03 2018
@@ -45,13 +45,11 @@ void RegisterFile::initialize(const MCSc
// object. The size of every register file, as well as the mapping between
// register files and register classes is specified via tablegen.
const MCExtraProcessorInfo &Info = SM.getExtraProcessorInfo();
- for (unsigned I = 0, E = Info.NumRegisterFiles; I < E; ++I) {
+
+ // Skip invalid register file at index 0.
+ for (unsigned I = 1, E = Info.NumRegisterFiles; I < E; ++I) {
const MCRegisterFileDesc &RF = Info.RegisterFiles[I];
- // Skip invalid register files with zero physical registers.
- // TODO: verify this constraint in SubtargetEmitter, and convert this
- // statement into an assert.
- if (!RF.NumPhysRegs)
- continue;
+ assert(RF.NumPhysRegs && "Invalid PRF with zero physical registers!");
// The cost of a register definition is equivalent to the number of
// physical registers that are allocated at register renaming stage.
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=344235&r1=344234&r2=344235&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Thu Oct 11 03:39:03 2018
@@ -1763,6 +1763,11 @@ void CodeGenSchedModels::collectRegister
// Now set the number of physical registers as well as the cost of registers
// in each register class.
CGRF.NumPhysRegs = RF->getValueAsInt("NumPhysRegs");
+ if (!CGRF.NumPhysRegs) {
+ PrintFatalError(RF->getLoc(),
+ "Invalid RegisterFile with zero physical registers");
+ }
+
RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
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