[llvm] r344211 - [WebAssembly][NFC] Use intrinsic dag nodes directly
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 10 17:49:24 PDT 2018
Author: tlively
Date: Wed Oct 10 17:49:24 2018
New Revision: 344211
URL: http://llvm.org/viewvc/llvm-project?rev=344211&view=rev
Log:
[WebAssembly][NFC] Use intrinsic dag nodes directly
Summary: Instead of custom lowering to WebAssemblyISD nodes first.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53119
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def?rev=344211&r1=344210&r2=344211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def Wed Oct 10 17:49:24 2018
@@ -22,12 +22,5 @@ HANDLE_NODETYPE(Wrapper)
HANDLE_NODETYPE(BR_IF)
HANDLE_NODETYPE(BR_TABLE)
HANDLE_NODETYPE(SHUFFLE)
-HANDLE_NODETYPE(ANYTRUE)
-HANDLE_NODETYPE(ALLTRUE)
-HANDLE_NODETYPE(BITSELECT)
-HANDLE_NODETYPE(ADD_SAT_S)
-HANDLE_NODETYPE(ADD_SAT_U)
-HANDLE_NODETYPE(SUB_SAT_S)
-HANDLE_NODETYPE(SUB_SAT_U)
// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=344211&r1=344210&r2=344211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Wed Oct 10 17:49:24 2018
@@ -966,44 +966,6 @@ WebAssemblyTargetLowering::LowerINTRINSI
default:
return {}; // Don't custom lower most intrinsics.
- case Intrinsic::wasm_add_saturate_signed:
- case Intrinsic::wasm_add_saturate_unsigned:
- case Intrinsic::wasm_sub_saturate_signed:
- case Intrinsic::wasm_sub_saturate_unsigned: {
- unsigned OpCode;
- switch (IntNo) {
- case Intrinsic::wasm_add_saturate_signed:
- OpCode = WebAssemblyISD::ADD_SAT_S;
- break;
- case Intrinsic::wasm_add_saturate_unsigned:
- OpCode = WebAssemblyISD::ADD_SAT_U;
- break;
- case Intrinsic::wasm_sub_saturate_signed:
- OpCode = WebAssemblyISD::SUB_SAT_S;
- break;
- case Intrinsic::wasm_sub_saturate_unsigned:
- OpCode = WebAssemblyISD::SUB_SAT_U;
- break;
- default:
- llvm_unreachable("unexpected intrinsic id");
- break;
- }
- return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1),
- Op.getOperand(2));
- }
-
- case Intrinsic::wasm_bitselect:
- return DAG.getNode(WebAssemblyISD::BITSELECT, DL, Op.getValueType(),
- Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
-
- case Intrinsic::wasm_anytrue:
- case Intrinsic::wasm_alltrue: {
- unsigned OpCode = IntNo == Intrinsic::wasm_anytrue
- ? WebAssemblyISD::ANYTRUE
- : WebAssemblyISD::ALLTRUE;
- return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1));
- }
-
case Intrinsic::wasm_lsda:
// TODO For now, just return 0 not to crash
return DAG.getConstant(0, DL, Op.getValueType());
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=344211&r1=344210&r2=344211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Wed Oct 10 17:49:24 2018
@@ -382,7 +382,9 @@ multiclass SIMDBinary<ValueType vec_t, s
bits<32> simdop> {
defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
- [(set (vec_t V128:$dst), (node V128:$lhs, V128:$rhs))],
+ [(set (vec_t V128:$dst),
+ (node (vec_t V128:$lhs), (vec_t V128:$rhs))
+ )],
vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
simdop>;
}
@@ -434,23 +436,19 @@ multiclass SIMDBinarySat<SDNode node, st
defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 2)>;
}
-def wasm_saturate_t : SDTypeProfile<1, 2,
- [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]
->;
-def wasm_add_sat_s : SDNode<"WebAssemblyISD::ADD_SAT_S", wasm_saturate_t>;
-def wasm_add_sat_u : SDNode<"WebAssemblyISD::ADD_SAT_U", wasm_saturate_t>;
-def wasm_sub_sat_s : SDNode<"WebAssemblyISD::SUB_SAT_S", wasm_saturate_t>;
-def wasm_sub_sat_u : SDNode<"WebAssemblyISD::SUB_SAT_U", wasm_saturate_t>;
-
// Saturating integer addition: add_saturate_s / add_saturate_u
let isCommutable = 1 in {
-defm ADD_SAT_S : SIMDBinarySat<wasm_add_sat_s, "add_saturate_s", 40>;
-defm ADD_SAT_U : SIMDBinarySat<wasm_add_sat_u, "add_saturate_u", 41>;
+defm ADD_SAT_S :
+ SIMDBinarySat<int_wasm_add_saturate_signed, "add_saturate_s", 40>;
+defm ADD_SAT_U :
+ SIMDBinarySat<int_wasm_add_saturate_unsigned, "add_saturate_u", 41>;
} // isCommutable = 1
// Saturating integer subtraction: sub_saturate_s / sub_saturate_u
-defm SUB_SAT_S : SIMDBinarySat<wasm_sub_sat_s, "sub_saturate_s", 44>;
-defm SUB_SAT_U : SIMDBinarySat<wasm_sub_sat_u, "sub_saturate_u", 45>;
+defm SUB_SAT_S :
+ SIMDBinarySat<int_wasm_sub_saturate_signed, "sub_saturate_s", 44>;
+defm SUB_SAT_U :
+ SIMDBinarySat<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 45>;
//===----------------------------------------------------------------------===//
// Bit shifts
@@ -518,16 +516,11 @@ defm "" : SIMDNot<v4i32>;
defm "" : SIMDNot<v2i64>;
// Bitwise select: v128.bitselect
-def wasm_bitselect_t : SDTypeProfile<1, 3,
- [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]
->;
-def wasm_bitselect : SDNode<"WebAssemblyISD::BITSELECT", wasm_bitselect_t>;
-
multiclass Bitselect<ValueType vec_t> {
defm BITSELECT_#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
[(set (vec_t V128:$dst),
- (vec_t (wasm_bitselect
+ (vec_t (int_wasm_bitselect
(vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2)
))
)],
@@ -562,15 +555,11 @@ multiclass SIMDReduce<string name, SDNod
defm "" : SIMDReduceVec<v2i64, "i64x2", name, op, !add(baseInst, 3)>;
}
-def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
-
// Any lane true: any_true
-def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
-defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
+defm ANYTRUE : SIMDReduce<"any_true", int_wasm_anytrue, 65>;
// All lanes true: all_true
-def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
-defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
+defm ALLTRUE : SIMDReduce<"all_true", int_wasm_alltrue, 69>;
//===----------------------------------------------------------------------===//
// Comparisons
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