[PATCH] D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

I've noticed that the bitcasts we introduce for these make computeKnownBits and computeNumSignBits not work well in LegalizeVectorOps. LegalizeVectorOps legalizes bottom up while LegalizeDAG legalizes top down. The bottom up strategy for LegalizeVectorOps means operands are legalized before their uses. So we promote and/or/xor before we legalize the operands that use them making computeKnownBits/computeNumSignBits in places like LowerTruncate suboptimal. I looked at changing LegalizeVectorOps to be top down as well, but that was more disruptive and caused some regressions. I also looked at just moving promotion of binops to LegalizeDAG, but that had a few issues one around matching AND,ANDN,OR into VSELECT because I had to create ANDN as vXi64, but the other nodes hadn't legalized yet, I didn't look too hard at fixing that.

This patch seems to produce better results overall than my other attempts. We now form broadcasts of constants better in some cases. For at least some of them the AND was being introduced in LegalizeDAG, promoted to vXi64, and the BUILD_VECTOR was also legalized there. I think we got bad ordering of that. Now the promotion is out of the legalizer so we handle this better.

In the longer term I think we really should evaluate whether we should be doing this promotion at all. It's really there to reduce isel pattern count, but I'm wondering if we'd be better served just eating the pattern cost or doing C++ based isel for vector and/or/xor in X86ISelDAGToDAG. The masked and/or/xor will definitely be difficult in patterns if a bitcast gets between the vselect and the and/or/xor node. That becomes a lot of permutations to cover.


https://reviews.llvm.org/D53107

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx-logic.ll
  test/CodeGen/X86/avx512-ext.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-schedule.ll
  test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  test/CodeGen/X86/cast-vsel.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-srl.ll
  test/CodeGen/X86/gather-addresses.ll
  test/CodeGen/X86/horizontal-reduce-umax.ll
  test/CodeGen/X86/horizontal-reduce-umin.ll
  test/CodeGen/X86/known-bits.ll
  test/CodeGen/X86/nontemporal-loads.ll
  test/CodeGen/X86/paddus.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/setcc-lowering.ll
  test/CodeGen/X86/sse2-intrinsics-canonical.ll
  test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
  test/CodeGen/X86/v8i1-masks.ll
  test/CodeGen/X86/vector-blend.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll
  test/CodeGen/X86/vector-shift-shl-128.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-trunc-math.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-trunc-usat.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/vshift-6.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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