[PATCH] D53080: [X86] X86ISelLowering: combineAndIntoBEXTR(): support shifted mask.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, spatel.

Continuation of https://reviews.llvm.org/D52426.

As discussed in PR38938 <https://bugs.llvm.org/show_bug.cgi?id=38938>,
we fail to emit `BEXTR` if the mask is shifted.
We can't deal with that in `X86DAGToDAGISel` `before the address mode for the inc is selected`,
and we can't really do it in the normal DAGCombine, because we don't have generic `ISD::BitFieldExtract` node,
and if we simply turn the shifted mask into a normal mask + shift-left, it will be folded back.
So it would seem X86ISelLowering is the place to handle this.

Here, we extend the combine to actually support the pattern with shifted mask.


Repository:
  rL LLVM

https://reviews.llvm.org/D53080

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/bmi-x86_64.ll
  test/CodeGen/X86/extract-bits.ll

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