[PATCH] D52932: [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

Clement Courbet via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 9 06:01:38 PDT 2018


courbet added a comment.

Hi Andrea, thanks for the comments.

I think there are two independent points that we're discussing here:
1 - Where we're putting the generated table
2 - How we specify the table.

Regarding (1):
The goal of this patch is to move the pfm counters out of the SchedModels (see PR39165), because different CPUs with different PFM counters can use the same sched model (e.g. sandybridge).
That being said, I'm not opposed to moving the table of CPU->`MCPfmCountersInfo` outside of the MCSubtargetInfo. One possible approach is to create a new `PfmEmitter` tablegen backend and PfmCounters library. If people think that's reasonable I can do that easily.

Regarding (2), I'm not sure I understand extactly what you're suggesting. Are you suggesting I do something like:

  let PfmCounters = HaswellPfmCounters in {
  def : HaswellProc<"haswell">;
  def : HaswellProc<"core-avx2">; // Legacy alias.
  }

Or more like:

  // In X86.td:
  def HaswellProcessorModel : HaswellProc<"haswell">;
  def CoreAvx2ProcessorModel : HaswellProc<"core-avx2">; // Legacy alias.
  
  // In X86PfmCounters.td:
  def : ProcPfmCounters {
    let CycleCounter = UnhaltedCoreCyclesPfmCounter;
    let UopsCounter = UopsIssuedPfmCounter;
    let IssueCounters = [
      PfmIssueCounter<"HWPort0", "uops_dispatched_port:port_0">,
      PfmIssueCounter<"HWPort1", "uops_dispatched_port:port_1">,
      PfmIssueCounter<"HWPort2", "uops_dispatched_port:port_2">,
      PfmIssueCounter<"HWPort3", "uops_dispatched_port:port_3">,
      PfmIssueCounter<"HWPort4", "uops_dispatched_port:port_4">,
      PfmIssueCounter<"HWPort5", "uops_dispatched_port:port_5">,
      PfmIssueCounter<"HWPort6", "uops_dispatched_port:port_6">,
      PfmIssueCounter<"HWPort7", "uops_dispatched_port:port_7">
    ];
    let ProcModels = [HaswellProcessorModel, CoreAvx2ProcessorModel]
  }




Repository:
  rL LLVM

https://reviews.llvm.org/D52932





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