[PATCH] D52816: [AArch64] Create proper memoperand for multi-vector stores

[David Greene via Phabricator via llvm-commits]

greened added inline comments.


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Comment at: test/CodeGen/AArch64/multi-vector-store-size.ll:69
+  tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
+; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})
+  tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
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efriedma wrote:
> I'm pretty sure these numbers aren't right.  You don't have to fix it here, necessarily; being overconservative isn't really a big deal.  But it would be nice to have a note in the testcase.
Yeah, there's an explicit comment in the lowering code about being conservative.  I'll add a similar comment to the test.


Repository:
  rL LLVM

https://reviews.llvm.org/D52816