[PATCH] D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:274
 
+bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
+  return SrcVT == MVT::i32 && DstVT == MVT::i64;
----------------
Should
```
if (!Subtarget.is64Bit())
    return false;
```
be added here? i64 shouldn't make it this far on 32 bit but is it better to be explicit?


https://reviews.llvm.org/D52978