[PATCH] D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: apazos, sameer.abuasal, shiva0217.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.

As discussed in the RFC <http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit RISC-V has i64 as the only legal integer type. This patch introduces patterns to support codegen of the new instructions introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw, sraiw, ld, sd.

Custom selection code is needed for srliw as SimplifyDemandedBits will remove lower bits from the mask, meaning the obvious pattern won't work:

  def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32),
            (SRLIW GPR:$rs1, uimm5:$shamt)>;

This is sufficient to compile and execute all of the GCC torture suite for RV64I other than those files using frameaddr or returnaddr intrinsics (LegalizeDAG doesn't know how to promote the operands - a future patch addresses this).

When promoting i32 sltu/sltiu operands, it would be more efficient to use sign-extension rather than zero-extension for RV64. A future patch adds a hook to allow this.


https://reviews.llvm.org/D52977

Files:
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/alu16.ll
  test/CodeGen/RISCV/alu32.ll
  test/CodeGen/RISCV/alu64.ll
  test/CodeGen/RISCV/alu8.ll
  test/CodeGen/RISCV/mem64.ll
  test/CodeGen/RISCV/sext-zext-trunc.ll

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