[llvm] r343960 - [ARM] Account for implicit IT when calculating inline asm size
Peter Smith via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 8 02:38:28 PDT 2018
Author: psmith
Date: Mon Oct 8 02:38:28 2018
New Revision: 343960
URL: http://llvm.org/viewvc/llvm-project?rev=343960&view=rev
Log:
[ARM] Account for implicit IT when calculating inline asm size
When deciding if it is safe to optimize a conditional branch to a CBZ or
CBNZ the offsets of the BasicBlocks from the start of the function are
estimated. For inline assembly the generic getInlineAsmLength() function is
used to get a worst case estimate of the inline assembly by multiplying the
number of instructions by the max instruction size of 4 bytes. This
unfortunately doesn't take into account the generation of Thumb implicit IT
instructions. In edge cases such as when all the instructions in the block
are 4-bytes in size and there is an implicit IT then the size is
underestimated. This can cause an out of range CBZ or CBNZ to be generated.
The patch takes a conservative approach and assumes that every instruction
in the inline assembly block may have an implicit IT.
Fixes pr31805
Differential Revision: https://reviews.llvm.org/D52834
Added:
llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=343960&r1=343959&r2=343960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 8 02:38:28 2018
@@ -708,8 +708,12 @@ unsigned ARMBaseInstrInfo::getInstSizeIn
return MCID.getSize();
// If this machine instr is an inline asm, measure it.
- if (MI.getOpcode() == ARM::INLINEASM)
- return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
+ if (MI.getOpcode() == ARM::INLINEASM) {
+ unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
+ if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction())
+ Size = alignTo(Size, 4);
+ return Size;
+ }
unsigned Opc = MI.getOpcode();
switch (Opc) {
default:
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp?rev=343960&r1=343959&r2=343960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp Mon Oct 8 02:38:28 2018
@@ -31,6 +31,9 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(c
SupportsDebugInformation = true;
+ // Conditional Thumb 4-byte instructions can have an implicit IT.
+ MaxInstLength = 6;
+
// Exceptions handling
ExceptionsType = (TheTriple.isOSDarwin() && !TheTriple.isWatchABI())
? ExceptionHandling::SjLj
@@ -56,6 +59,9 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const T
SupportsDebugInformation = true;
+ // Conditional Thumb 4-byte instructions can have an implicit IT.
+ MaxInstLength = 6;
+
// Exceptions handling
switch (TheTriple.getOS()) {
case Triple::NetBSD:
@@ -90,6 +96,9 @@ ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmI
PrivateGlobalPrefix = "$M";
PrivateLabelPrefix = "$M";
CommentString = ";";
+
+ // Conditional Thumb 4-byte instructions can have an implicit IT.
+ MaxInstLength = 6;
}
void ARMCOFFMCAsmInfoGNU::anchor() { }
@@ -110,5 +119,7 @@ ARMCOFFMCAsmInfoGNU::ARMCOFFMCAsmInfoGNU
UseIntegratedAssembler = true;
DwarfRegNumForCFI = false;
-}
+ // Conditional Thumb 4-byte instructions can have an implicit IT.
+ MaxInstLength = 6;
+}
Added: llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll?rev=343960&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll Mon Oct 8 02:38:28 2018
@@ -0,0 +1,47 @@
+;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -arm-implicit-it=always %s -o - | FileCheck %s
+;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -no-integrated-as %s -o - | FileCheck %s
+
+; Check that we do not produce a CBZ instruction to jump over the inline
+; assembly as the distance is too far if the implicit IT instructions are
+; added.
+
+define void @f0(i32 %p1, i32 %p2, i32 %p3) nounwind {
+entry:
+ %cmp = icmp eq i32 %p1, 0
+ br i1 %cmp, label %if.else, label %if.then
+
+if.then:
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ br label %if.end
+
+if.else:
+ tail call void asm sideeffect "nop\0A", ""()
+ br label %if.end
+
+if.end:
+ ret void
+}
+; CHECK-LABEL: f0:
+; CHECK: beq .LBB0_{{[0-9]+}}
+
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