[PATCH] D52964: [x86] use demanded bits to simplify masked store codegen

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, andreadb.
Herald added a subscriber: mcrosier.

As noted in https://reviews.llvm.org/D52747, if we prefer IR to use trunc for bool vectors rather than and+icmp, we can expose codegen shortcomings as seen here with masked store.

We can replace a hard-coded PCMPGT simplification with the more general demanded bits call here to improve things. The AVX1 pattern still isn't handled, so that's another potential dependency for the instcombine patch (although I'm not sure how much masked op usage we prefer with only AVX1).


https://reviews.llvm.org/D52964

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/masked_memop.ll

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