[PATCH] D52948: [WebAssembly] Fix fneg lowering

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added reviewers: aheejin, dschuff.
Herald added subscribers: llvm-commits, sunfish, jgravelle-google, sbc100.

Subtraction from zero and floating point negation do not have the same
semantics, so fix lowering.


Repository:
  rL LLVM

https://reviews.llvm.org/D52948

Files:
  lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  test/CodeGen/WebAssembly/simd-arith.ll


Index: test/CodeGen/WebAssembly/simd-arith.ll
===================================================================
--- test/CodeGen/WebAssembly/simd-arith.ll
+++ test/CodeGen/WebAssembly/simd-arith.ll
@@ -744,7 +744,7 @@
 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @neg_v4f32(<4 x float> %x) {
-  %a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
+  %a = fsub fast <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x
   ret <4 x float> %a
 }
 
@@ -826,7 +826,7 @@
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @neg_v2f64(<2 x double> %x) {
-  %a = fsub <2 x double> <double 0., double 0.>, %x
+  %a = fsub fast <2 x double> <double 0., double 0.>, %x
   ret <2 x double> %a
 }
 
Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -173,28 +173,23 @@
   defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
 }
-multiclass SIMDNeg<ValueType vec_t, string vec, PatFrag splat_pat,
-                   ValueType lane_t, SDNode node, dag lane, bits<32> simdop> {
+multiclass SIMDNegInt<ValueType vec_t, string vec, bits<32> simdop> {
   defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
                            (outs), (ins),
                            [(set
                              (vec_t V128:$dst),
-                             (vec_t (node
-                               (vec_t (splat_pat lane)),
+                             (vec_t (sub
+                               (vec_t immAllZerosV),
                                (vec_t V128:$vec)
                              ))
                            )],
                            vec#".neg\t$dst, $vec", vec#".neg", simdop>;
 }
-multiclass SIMDNegInt<ValueType vec_t, string vec, PatFrag splat_pat,
-                      ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, sub, (lane_t 0), simdop>;
-}
-def fpimm0 : FPImmLeaf<fAny, [{ return Imm.isExactlyValue(+0.0); }]>;
-multiclass SIMDNegFP<ValueType vec_t, string vec, PatFrag splat_pat,
-                     ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, fsub, (lane_t fpimm0),
-                    simdop>;
+multiclass SIMDNegFP<ValueType vec_t, string vec, bits<32> simdop> {
+  defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
+                           (outs), (ins),
+                           [(set (vec_t V128:$dst), (vec_t (fneg V128:$vec)))],
+                           vec#".neg\t$dst, $vec", vec#".neg", simdop>;
 }
 multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
   defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
@@ -387,12 +382,12 @@
 defm SUB_SAT_U : SIMDBinarySat<wasm_sub_sat_u, "sub_saturate_u", 45>;
 defm DIV : SIMDBinaryFP<fdiv, "div", 137>;
 
-defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 36>;
-defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 37>;
-defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 38>;
-defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 39>;
-defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 125>;
-defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 126>;
+defm "" : SIMDNegInt<v16i8, "i8x16", 36>;
+defm "" : SIMDNegInt<v8i16, "i16x8", 37>;
+defm "" : SIMDNegInt<v4i32, "i32x4", 38>;
+defm "" : SIMDNegInt<v2i64, "i64x2", 39>;
+defm "" : SIMDNegFP<v4f32, "f32x4", 125>;
+defm "" : SIMDNegFP<v2f64, "f64x2", 126>;
 
 defm SHL : SIMDShiftInt<shl, "shl", 48, 0>;
 defm SHR_S : SIMDShiftInt<sra, "shr_s", 52, 1>;


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