[PATCH] D52922: AMDGPU/GlobalISel: Move SMRD selection logic to TableGen

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/AMDGPUGISel.td:153
+// Since GlobalISel is more flexible then SelectionDAG, I think we can get
+// away with adding patterns for integer types and not leaglizing all
+// loads and stores to vector types.  This should help simplify the load/store
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Typo leaglizing


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Comment at: lib/Target/AMDGPU/AMDGPUGISel.td:154-155
+// away with adding patterns for integer types and not leaglizing all
+// loads and stores to vector types.  This should help simplify the load/store
+// legalization.
+defm : SMRD_Pattern <"S_LOAD_DWORDX2",  i64>;
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I think turning everything into i32 vectors in SelectionDAG was a mistake, but I don't think GlobalISel will have the same issues with it. Floating point loads don't need to be explicitly handled anymore?


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Comment at: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:234-248
+  case TargetOpcode::G_LOAD: {
+    unsigned DstReg = MI.getOperand(0).getReg();
+    LLT LoadTy = MRI.getType(DstReg);
+    if (!LoadTy.isPointer())
+      return false;
+    unsigned LoadSize = LoadTy.getSizeInBits();
+    assert(LoadSize % 32 == 0);
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Why is this target specific?


Repository:
  rL LLVM

https://reviews.llvm.org/D52922