[PATCH] D52886: [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86SchedBroadwell.td:79
 
+// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 5/5/6 cycles after the memory operand.
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craig.topper wrote:
> The load latencies on BDW seem weird given that HSW and SKL, the CPUs immediately before and after are the same.
They're the same as BDW's load latencies - can we confirm if they are correct or not? I think this question has come up several times in the past....


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Comment at: lib/Target/X86/X86SchedSkylakeServer.td:74
 
-// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
+// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
 // cycles after the memory operand.
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craig.topper wrote:
> Why this comment only changed in this model? The same comment existing in SNB, HSW, BDW, and SKLClient.
Because my copy+paste skills are below average.


Repository:
  rL LLVM

https://reviews.llvm.org/D52886