[llvm] r343712 - [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection

[Alex Bradbury via llvm-commits]

On Thu, 4 Oct 2018 at 00:00, Friedman, Eli via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> On 10/3/2018 1:12 PM, Alex Bradbury via llvm-commits wrote:
> > Author: asb
> > Date: Wed Oct  3 13:12:10 2018
> > New Revision: 343712
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=343712&view=rev
> > Log:
> > [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection
> >
> > Although we can't write a tablegen pattern to remove redundant
> > splitf64+buildf64 pairs due to the multiple return values, we can handle it
> > with some C++ selection code. This is simpler than removing them after
> > instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was
> > done previously.
>
> Could you write this as a DAGCombine instead?  Might allow other
> optimizations.

Thanks Eli, that would indeed be better. I'm not seeing any codegen
differences from a quick run of the GCC torture suite, but as you say
this should expose more optimisation opportunities.

I've moved to using a DAGCombine in r343741.

Best,

Alex