[llvm] r343677 - [RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32

[Alex Bradbury via llvm-commits]

Author: asb
Date: Wed Oct  3 04:04:59 2018
New Revision: 343677

URL: http://llvm.org/viewvc/llvm-project?rev=343677&view=rev
Log:
[RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32

These patterns are not correct for RV64.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=343677&r1=343676&r2=343677&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Oct  3 04:04:59 2018
@@ -625,7 +625,8 @@ def IsOrAdd: PatFrag<(ops node:$A, node:
 
 def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
 def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>;
-def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
+def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>,
+      Requires<[IsRV32]>;
 
 /// Simple arithmetic operations
 
@@ -808,7 +809,7 @@ multiclass StPat<PatFrag StoreOp, RVInst
 
 defm : StPat<truncstorei8, SB, GPR>;
 defm : StPat<truncstorei16, SH, GPR>;
-defm : StPat<store, SW, GPR>;
+defm : StPat<store, SW, GPR>, Requires<[IsRV32]>;
 
 /// Fences