[PATCH] D52816: [AArch64] Create proper memoperand for multi-vector stores

[David Greene via Phabricator via llvm-commits]

greened created this revision.
greened added reviewers: niravd, trong, sdesmalen, nickdesaulniers, jfb, eli.friedman, mstorsjo, t.p.northover.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, kristof.beyls.

Include all of the store's source vector operands when creating the MachineMemOperand.  Previously, we were missing the first operand, making the store size seem smaller than it really is.


Repository:
  rL LLVM

https://reviews.llvm.org/D52816

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp


Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7868,7 +7868,7 @@
     Info.opc = ISD::INTRINSIC_VOID;
     // Conservatively set memVT to the entire set of vectors stored.
     unsigned NumElts = 0;
-    for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
+    for (unsigned ArgI = 0, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
       Type *ArgTy = I.getArgOperand(ArgI)->getType();
       if (!ArgTy->isVectorTy())
         break;


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