[llvm] r343649 - [WebAssembly] any_true and all_true intrinsics and instructions
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 2 17:19:39 PDT 2018
Author: tlively
Date: Tue Oct 2 17:19:39 2018
New Revision: 343649
URL: http://llvm.org/viewvc/llvm-project?rev=343649&view=rev
Log:
[WebAssembly] any_true and all_true intrinsics and instructions
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52755
Added:
llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/MC/WebAssembly/simd-encodings.s
Modified: llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td?rev=343649&r1=343648&r2=343649&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td Tue Oct 2 17:19:39 2018
@@ -87,4 +87,17 @@ def int_wasm_atomic_notify:
[IntrInaccessibleMemOnly, NoCapture<0>, IntrHasSideEffects], "",
[SDNPMemOperand]>;
-}
+//===----------------------------------------------------------------------===//
+// SIMD intrinsics
+//===----------------------------------------------------------------------===//
+
+def int_wasm_anytrue :
+ Intrinsic<[llvm_i32_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_alltrue :
+ Intrinsic<[llvm_i32_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+
+} // TargetPrefix = "wasm"
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def?rev=343649&r1=343648&r2=343649&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def Tue Oct 2 17:19:39 2018
@@ -22,5 +22,7 @@ HANDLE_NODETYPE(Wrapper)
HANDLE_NODETYPE(BR_IF)
HANDLE_NODETYPE(BR_TABLE)
HANDLE_NODETYPE(SHUFFLE)
+HANDLE_NODETYPE(ANYTRUE)
+HANDLE_NODETYPE(ALLTRUE)
// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=343649&r1=343648&r2=343649&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Tue Oct 2 17:19:39 2018
@@ -959,7 +959,13 @@ WebAssemblyTargetLowering::LowerINTRINSI
switch (IntNo) {
default:
return {}; // Don't custom lower most intrinsics.
-
+ case Intrinsic::wasm_anytrue:
+ case Intrinsic::wasm_alltrue: {
+ unsigned OpCode = IntNo == Intrinsic::wasm_anytrue
+ ? WebAssemblyISD::ANYTRUE
+ : WebAssemblyISD::ALLTRUE;
+ return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1));
+ }
case Intrinsic::wasm_lsda:
// TODO For now, just return 0 not to crash
return DAG.getConstant(0, DL, Op.getValueType());
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=343649&r1=343648&r2=343649&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Tue Oct 2 17:19:39 2018
@@ -18,6 +18,13 @@ def ImmI#SIZE : ImmLeaf<i32, "return (Im
foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
+// Custom nodes for custom operations
+def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
+def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
+def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
+def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
+def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
+
multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
let isMoveImm = 1, isReMaterializable = 1 in
defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
@@ -186,6 +193,18 @@ multiclass SIMDNot<ValueType vec_t, PatF
)],
"v128.not\t$dst, $vec", "v128.not", 63>;
}
+multiclass SIMDReduceVec<ValueType vec_t, string vec, string name, SDNode op,
+ bits<32> simdop> {
+ defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+ [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
+ vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
+}
+multiclass SIMDReduce<string name, SDNode op, bits<32> baseInst> {
+ defm "" : SIMDReduceVec<v16i8, "i8x16", name, op, baseInst>;
+ defm "" : SIMDReduceVec<v8i16, "i16x8", name, op, !add(baseInst, 1)>;
+ defm "" : SIMDReduceVec<v4i32, "i32x4", name, op, !add(baseInst, 2)>;
+ defm "" : SIMDReduceVec<v2i64, "i64x2", name, op, !add(baseInst, 3)>;
+}
multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
string name, CondCode cond, bits<32> simdop> {
defm _#vec_t :
@@ -361,6 +380,9 @@ defm "" : SIMDNot<v8i16, splat8, i32>;
defm "" : SIMDNot<v4i32, splat4, i32>;
defm "" : SIMDNot<v2i64, splat2, i64>;
+defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
+defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
+
let isCommutable = 1 in {
defm EQ : SIMDConditionInt<"eq", SETEQ, 73>;
defm EQ : SIMDConditionFP<"eq", SETOEQ, 77>;
@@ -457,8 +479,6 @@ def : Pat<(v2i64 (shifts[0] (v2i64 V128:
(v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
// Shuffles after custom lowering
-def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
-def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
def : Pat<(v16i8 (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
(i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
Added: llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll?rev=343649&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll Tue Oct 2 17:19:39 2018
@@ -0,0 +1,109 @@
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+
+; Test that SIMD128 intrinsics lower as expected. These intrinsics are
+; only expected to lower successfully if the simd128 attribute is
+; enabled and legal types are used.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; ==============================================================================
+; 16 x i8
+; ==============================================================================
+; CHECK-LABEL: any_v16i8:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
+define i32 @any_v16i8(<16 x i8> %x) {
+ %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
+ ret i32 %a
+}
+
+; CHECK-LABEL: all_v16i8:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
+define i32 @all_v16i8(<16 x i8> %x) {
+ %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
+ ret i32 %a
+}
+
+; ==============================================================================
+; 8 x i16
+; ==============================================================================
+; CHECK-LABEL: any_v8i16:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
+define i32 @any_v8i16(<8 x i16> %x) {
+ %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
+ ret i32 %a
+}
+
+; CHECK-LABEL: all_v8i16:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
+define i32 @all_v8i16(<8 x i16> %x) {
+ %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
+ ret i32 %a
+}
+
+; ==============================================================================
+; 4 x i32
+; ==============================================================================
+; CHECK-LABEL: any_v4i32:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
+define i32 @any_v4i32(<4 x i32> %x) {
+ %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
+ ret i32 %a
+}
+
+; CHECK-LABEL: all_v4i32:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
+define i32 @all_v4i32(<4 x i32> %x) {
+ %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
+ ret i32 %a
+}
+
+; ==============================================================================
+; 2 x i64
+; ==============================================================================
+; CHECK-LABEL: any_v2i64:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
+define i32 @any_v2i64(<2 x i64> %x) {
+ %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
+ ret i32 %a
+}
+
+; CHECK-LABEL: all_v2i64:
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result i32{{$}}
+; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
+define i32 @all_v2i64(<2 x i64> %x) {
+ %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
+ ret i32 %a
+}
Modified: llvm/trunk/test/MC/WebAssembly/simd-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/WebAssembly/simd-encodings.s?rev=343649&r1=343648&r2=343649&view=diff
==============================================================================
--- llvm/trunk/test/MC/WebAssembly/simd-encodings.s (original)
+++ llvm/trunk/test/MC/WebAssembly/simd-encodings.s Tue Oct 2 17:19:39 2018
@@ -193,6 +193,30 @@
# CHECK: v128.not # encoding: [0xfd,0x3f]
v128.not
+ # CHECK: i8x16.any_true # encoding: [0xfd,0x41]
+ i8x16.any_true
+
+ # CHECK: i16x8.any_true # encoding: [0xfd,0x42]
+ i16x8.any_true
+
+ # CHECK: i32x4.any_true # encoding: [0xfd,0x43]
+ i32x4.any_true
+
+ # CHECK: i64x2.any_true # encoding: [0xfd,0x44]
+ i64x2.any_true
+
+ # CHECK: i8x16.all_true # encoding: [0xfd,0x45]
+ i8x16.all_true
+
+ # CHECK: i16x8.all_true # encoding: [0xfd,0x46]
+ i16x8.all_true
+
+ # CHECK: i32x4.all_true # encoding: [0xfd,0x47]
+ i32x4.all_true
+
+ # CHECK: i64x2.all_true # encoding: [0xfd,0x48]
+ i64x2.all_true
+
# CHECK: i8x16.eq # encoding: [0xfd,0x49]
i8x16.eq
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