[llvm] r343487 - [X86] Remove unnecessary BTmi/BTmr scheduler overrides
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 1 08:01:01 PDT 2018
Author: rksimon
Date: Mon Oct 1 08:01:00 2018
New Revision: 343487
URL: http://llvm.org/viewvc/llvm-project?rev=343487&view=rev
Log:
[X86] Remove unnecessary BTmi/BTmr scheduler overrides
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (contents, props changed)
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (contents, props changed)
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Oct 1 08:01:00 2018
@@ -978,13 +978,6 @@ def BWWriteResGroup62 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup62], (instrs FARJMP64)>;
def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
-def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
-
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
let NumMicroOps = 2;
Propchange: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
------------------------------------------------------------------------------
--- svn:executable (original)
+++ svn:executable (removed)
@@ -1 +0,0 @@
-*
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Oct 1 08:01:00 2018
@@ -168,8 +168,8 @@ def : WriteRes<WriteSETCCStore, [HWPort
defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestImmLd, [HWPort06], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestRegLd, [HWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;
defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
@@ -645,13 +645,6 @@ def : InstRW<[HWWritePopA], (instregex "
//-- Arithmetic instructions --//
-// BT.
-// m,r.
-def HWWriteBTmr : SchedWriteRes<[]> {
- let NumMicroOps = 10;
-}
-def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>;
-
// BTR BTS BTC.
// m,r.
def HWWriteBTRSCmr : SchedWriteRes<[]> {
@@ -994,13 +987,6 @@ def HWWriteResGroup14 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup14], (instrs FARJMP64)>;
def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
-def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
-
def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
let Latency = 6;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Oct 1 08:01:00 2018
@@ -163,8 +163,8 @@ def : WriteRes<WriteSETCCStore, [SBPort
defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestImmLd, [SBPort05], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestRegLd, [SBPort05], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
@@ -817,13 +817,6 @@ def SBWriteResGroup49 : SchedWriteRes<[S
}
def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
-def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>;
-
def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 6;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Oct 1 08:01:00 2018
@@ -1018,13 +1018,6 @@ def SKLWriteResGroup72 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>;
def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
-def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
-
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Oct 1 08:01:00 2018
@@ -1177,13 +1177,6 @@ def SKXWriteResGroup76 : SchedWriteRes<[
def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
-def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
-
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
let NumMicroOps = 2;
Propchange: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
------------------------------------------------------------------------------
--- svn:executable (original)
+++ svn:executable (removed)
@@ -1 +0,0 @@
-*
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Mon Oct 1 08:01:00 2018
@@ -121,10 +121,10 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort
let Latency = 2;
let ResourceCycles = [2];
}
-defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestRegLd, [AtomPort0], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;
+defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [AtomPort1]>;
@@ -628,8 +628,7 @@ def AtomWrite01_9 : SchedWriteRes<[AtomP
let Latency = 9;
let ResourceCycles = [9];
}
-def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr,
- POPA16, POPA32,
+def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
PUSHF16, PUSHF32, PUSHF64,
SHLD64mrCL, SHRD64mrCL,
SHLD64mri8, SHRD64mri8,
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=343487&r1=343486&r2=343487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Mon Oct 1 08:01:00 2018
@@ -714,10 +714,6 @@ def ZnWriteALULat2Ld : SchedWriteRes<[Zn
let Latency = 6;
}
-// BT.
-// m,i.
-def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
-
// BTR BTS BTC.
// m,r,i.
def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> {
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