[llvm] r343264 - AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 27 13:49:00 PDT 2018
Author: kzhuravl
Date: Thu Sep 27 13:49:00 2018
New Revision: 343264
URL: http://llvm.org/viewvc/llvm-project?rev=343264&view=rev
Log:
AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=343264&r1=343263&r2=343264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Thu Sep 27 13:49:00 2018
@@ -1710,7 +1710,9 @@ class VOPProfile <list<ValueType> _ArgVT
field bit HasSDWAOMod = isFloatType<DstVT>.ret;
field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
- field bit HasSDWA9 = HasExt;
+ field bit HasExtDPP = HasExt;
+ field bit HasExtSDWA = HasExt;
+ field bit HasExtSDWA9 = HasExt;
field int NeedPatGen = PatGenMode.NoPattern;
field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
@@ -1761,7 +1763,9 @@ class VOPProfile <list<ValueType> _ArgVT
class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
let HasExt = 0;
- let HasSDWA9 = 0;
+ let HasExtDPP = 0;
+ let HasExtSDWA = 0;
+ let HasExtSDWA9 = 0;
}
class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.Pattern> : VOPProfile <p.ArgVT> {
Modified: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td?rev=343264&r1=343263&r2=343264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td Thu Sep 27 13:49:00 2018
@@ -242,7 +242,9 @@ def VOP_I32_VI32_NO_EXT : VOPProfile<[i3
let Src0RC64 = VRegSrc_32;
let HasExt = 0;
- let HasSDWA9 = 0;
+ let HasExtDPP = 0;
+ let HasExtSDWA = 0;
+ let HasExtSDWA9 = 0;
}
// Special case because there are no true output operands. Hack vdst
@@ -271,7 +273,10 @@ def VOP_MOVRELD : VOPProfile<[untyped, i
let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
let HasExt = 0;
- let HasSDWA9 = 0;
+ let HasExtDPP = 0;
+ let HasExtSDWA = 0;
+ let HasExtSDWA9 = 0;
+
let HasDst = 0;
let EmitDst = 1; // force vdst emission
}
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=343264&r1=343263&r2=343264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Thu Sep 27 13:49:00 2018
@@ -252,8 +252,11 @@ class VOP_MAC <ValueType vt> : VOPProfil
let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret;
let HasSrc2 = 0;
let HasSrc2Mods = 0;
+
let HasExt = 1;
- let HasSDWA9 = 0;
+ let HasExtDPP = 1;
+ let HasExtSDWA = 1;
+ let HasExtSDWA9 = 0;
}
def VOP_MAC_F16 : VOP_MAC <f16>;
@@ -303,7 +306,9 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
let HasExt = 1;
- let HasSDWA9 = 1;
+ let HasExtDPP = 1;
+ let HasExtSDWA = 1;
+ let HasExtSDWA9 = 1;
}
// Read in from vcc or arbitrary SGPR
@@ -334,7 +339,9 @@ def VOP2e_I32_I32_I32_I1 : VOPProfile<[i
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
let HasExt = 1;
- let HasSDWA9 = 1;
+ let HasExtDPP = 1;
+ let HasExtSDWA = 1;
+ let HasExtSDWA9 = 1;
}
def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
@@ -344,8 +351,11 @@ def VOP_READLANE : VOPProfile<[i32, i32,
let Ins64 = Ins32;
let Asm32 = " $vdst, $src0, $src1";
let Asm64 = Asm32;
+
let HasExt = 0;
- let HasSDWA9 = 0;
+ let HasExtDPP = 0;
+ let HasExtSDWA = 0;
+ let HasExtSDWA9 = 0;
}
def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
@@ -355,10 +365,13 @@ def VOP_WRITELANE : VOPProfile<[i32, i32
let Ins64 = Ins32;
let Asm32 = " $vdst, $src0, $src1";
let Asm64 = Asm32;
- let HasExt = 0;
- let HasSDWA9 = 0;
let HasSrc2 = 0;
let HasSrc2Mods = 0;
+
+ let HasExt = 0;
+ let HasExtDPP = 0;
+ let HasExtSDWA = 0;
+ let HasExtSDWA9 = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=343264&r1=343263&r2=343264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td Thu Sep 27 13:49:00 2018
@@ -420,10 +420,10 @@ class VOP_SDWA_Pseudo <string opName, VO
let SDWA = 1;
let Uses = [EXEC];
- let SubtargetPredicate = !if(P.HasExt, HasSDWA, DisableInst);
- let AssemblerPredicate = !if(P.HasExt, HasSDWA, DisableInst);
- let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.SDWA,
- AMDGPUAsmVariants.Disable);
+ let SubtargetPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
+ let AssemblerPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
+ let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
+ AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA";
VOPProfile Pfl = P;
@@ -471,10 +471,10 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
- let SubtargetPredicate = !if(ps.Pfl.HasSDWA9, HasSDWA9, DisableInst);
- let AssemblerPredicate = !if(ps.Pfl.HasSDWA9, HasSDWA9, DisableInst);
- let AsmVariantName = !if(ps.Pfl.HasSDWA9, AMDGPUAsmVariants.SDWA9,
- AMDGPUAsmVariants.Disable);
+ let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
+ let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
+ let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
+ AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA9";
// Copy relevant pseudo op flags
@@ -520,9 +520,9 @@ class VOP_DPP <string OpName, VOPProfile
let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
let SubtargetPredicate = HasDPP;
- let AssemblerPredicate = !if(P.HasExt, HasDPP, DisableInst);
- let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
- AMDGPUAsmVariants.Disable);
+ let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
+ let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
+ AMDGPUAsmVariants.Disable);
let Constraints = !if(P.NumSrcArgs, "$old = $vdst", "");
let DisableEncoding = !if(P.NumSrcArgs, "$old", "");
let DecoderNamespace = "DPP";
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