[PATCH] D52483: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB

[Tim Northover via Phabricator via llvm-commits]

t.p.northover accepted this revision.
t.p.northover added a comment.
This revision is now accepted and ready to land.

Thanks for the clarification. LGTM.



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Comment at: lib/Target/AArch64/AArch64InstrInfo.td:648-649
 def : InstAlias<"isb", (ISB 0xf)>;
+def : InstAlias<"ssbb", (DSB 0)>;
+def : InstAlias<"pssbb", (DSB 4)>;
 
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olista01 wrote:
> t.p.northover wrote:
> > I think these should have `Predicates` set since not all CPUs support them.
> This is deliberate, these instructions have been retroactively added to v8.0-A onwards. This works because they are aliases for "DSB #0" and "DSB #4", which older specs say have to behave like "DSB SY", which has stronger semantics than SSBB and PSSBB. This means that existing cores already implement these, though in a more costly way than v8.5-A allows.
OK, I wondered if it was something like that but the manual was a bit vague on the topic and I wasn't certain the existing DSB sufficed.


Repository:
  rL LLVM

https://reviews.llvm.org/D52483