[llvm] r343216 - [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 27 06:53:35 PDT 2018
Author: olista01
Date: Thu Sep 27 06:53:35 2018
New Revision: 343216
URL: http://llvm.org/viewvc/llvm-project?rev=343216&view=rev
Log:
[AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction
This adds a new variant of the DC system instruction for persistent
memory.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52480
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-persistent-memory.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Sep 27 06:53:35 2018
@@ -217,6 +217,9 @@ def FeatureSpecCtrl : SubtargetFeature<"
def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
"Enable execution and data prediction invalidation instructions" >;
+def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
+ "true", "Enable Cache Clean to Point of Deep Persistence" >;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -236,7 +239,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecCtrl,
- FeaturePredCtrl]
+ FeaturePredCtrl, FeatureCacheDeepPersist]
>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Sep 27 06:53:35 2018
@@ -70,6 +70,8 @@ def HasSpecCtrl : Predicate<"Subtar
AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
+def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
+ AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def UseAlternateSExtLoadCVTF32
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Sep 27 06:53:35 2018
@@ -99,6 +99,7 @@ protected:
bool HasFRInt3264 = false;
bool HasSpecCtrl = false;
bool HasPredCtrl = false;
+ bool HasCCDP = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
@@ -316,6 +317,7 @@ public:
bool hasFRInt3264() const { return HasFRInt3264; }
bool hasSpecCtrl() { return HasSpecCtrl; }
bool hasPredCtrl() { return HasPredCtrl; }
+ bool hasCCDP() { return HasCCDP; }
bool isLittleEndian() const { return IsLittle; }
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Thu Sep 27 06:53:35 2018
@@ -105,6 +105,9 @@ def : DC<"CISW", 0b000, 0b0111, 0b1110,
let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
+let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
+def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;
+
//===----------------------------------------------------------------------===//
// IC (instruction cache maintenance) instruction options.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Thu Sep 27 06:53:35 2018
@@ -2757,6 +2757,7 @@ static const struct Extension {
{ "ras", {AArch64::FeatureRAS} },
{ "lse", {AArch64::FeatureLSE} },
{ "predctrl", {AArch64::FeaturePredCtrl} },
+ { "ccdp", {AArch64::FeatureCacheDeepPersist} },
// FIXME: Unsupported extensions
{ "pan", {} },
Modified: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp?rev=343216&r1=343215&r2=343216&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp Thu Sep 27 06:53:35 2018
@@ -812,7 +812,7 @@ bool AArch64InstPrinter::printSysAlias(c
}
break;
// DC aliases
- case 4: case 6: case 10: case 11: case 12: case 14:
+ case 4: case 6: case 10: case 11: case 12: case 13: case 14:
{
const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
Added: llvm/trunk/test/MC/AArch64/armv8.5a-persistent-memory.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-persistent-memory.s?rev=343216&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-persistent-memory.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-persistent-memory.s Thu Sep 27 06:53:35 2018
@@ -0,0 +1,7 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccdp < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-ccdp < %s 2>&1 | FileCheck %s --check-prefix=NOCCDP
+
+dc cvadp, x7
+// CHECK: dc cvadp, x7 // encoding: [0x27,0x7d,0x0b,0xd5]
+// NOCCDP: error: DC CVADP requires ccdp
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt?rev=343216&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-persistent-memory.txt Thu Sep 27 06:53:35 2018
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+ccdp --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.5a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-ccdp --disassemble < %s | FileCheck %s --check-prefix=NOCCDP
+
+[0x27,0x7d,0x0b,0xd5]
+# CHECK: dc cvadp, x7
+# NOCCDP: sys #3, c7, c13, #1, x7
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