[llvm] r343202 - [Sparc] Add support for the partial write PSR instruction
Daniel Cederman via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 27 05:34:48 PDT 2018
Author: dcederman
Date: Thu Sep 27 05:34:48 2018
New Revision: 343202
URL: http://llvm.org/viewvc/llvm-project?rev=343202&view=rev
Log:
[Sparc] Add support for the partial write PSR instruction
Summary:
Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR
instructions to only affect the %PSR.ET field. It is supported by
the GR740 and GR716.
Reviewers: jyknight, venkatra
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48644
Added:
llvm/trunk/test/MC/Sparc/leon-pwrpsr-instruction.s
Modified:
llvm/trunk/lib/Target/Sparc/Sparc.td
llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
Modified: llvm/trunk/lib/Target/Sparc/Sparc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.td?rev=343202&r1=343201&r2=343202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.td (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.td Thu Sep 27 05:34:48 2018
@@ -49,6 +49,9 @@ def FeatureVIS3
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
+def FeaturePWRPSR
+ : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true",
+ "Enable the PWRPSR instruction">;
def FeatureHardQuad
: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
@@ -159,7 +162,8 @@ def : Processor<"leon4", LEON4Itinerarie
// LEON 4 FT (GR740)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr740", LEON4Itineraries,
- [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter]>;
+ [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter,
+ FeaturePWRPSR]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td?rev=343202&r1=343201&r2=343202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td Thu Sep 27 05:34:48 2018
@@ -470,6 +470,8 @@ def : InstAlias<"wr $simm13, %wim", (WRW
def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
+def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
+def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
// flush -> flush %g0
def : InstAlias<"flush", (FLUSH), 0>;
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=343202&r1=343201&r2=343202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Thu Sep 27 05:34:48 2018
@@ -56,6 +56,11 @@ def HasHardQuad : Predicate<"Subtarget->
// instruction
def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
+// HasPWRPSR - This is true when the target processor supports partial
+// writes to the PSR register that only affects the ET field.
+def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
+ AssemblerPredicate<"FeaturePWRPSR">;
+
// HasUMAC_SMAC - This is true when the target processor supports the
// UMAC and SMAC instructions
def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
@@ -1587,6 +1592,17 @@ let Predicates = [HasUMAC_SMAC], Defs =
[], IIC_smac_umac>;
}
+// The partial write WRPSR instruction has a non-zero destination
+// register value to separate it from the standard instruction.
+let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in {
+ def PWRPSRrr : F3_1<2, 0b110001,
+ (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
+ "pwr $rs1, $rs2, %psr", []>;
+ def PWRPSRri : F3_2<2, 0b110001,
+ (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
+ "pwr $rs1, $simm13, %psr", []>;
+}
+
let Defs = [ICC] in {
defm TADDCC : F3_12np<"taddcc", 0b100000>;
defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=343202&r1=343201&r2=343202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Sep 27 05:34:48 2018
@@ -44,6 +44,7 @@ SparcSubtarget &SparcSubtarget::initiali
// Leon features
HasLeonCasa = false;
HasUmacSmac = false;
+ HasPWRPSR = false;
InsertNOPLoad = false;
FixAllFDIVSQRT = false;
DetectRoundChange = false;
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=343202&r1=343201&r2=343202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Thu Sep 27 05:34:48 2018
@@ -47,6 +47,7 @@ class SparcSubtarget : public SparcGenSu
// LEON features
bool HasUmacSmac;
bool HasLeonCasa;
+ bool HasPWRPSR;
bool InsertNOPLoad;
bool FixAllFDIVSQRT;
bool DetectRoundChange;
@@ -93,6 +94,7 @@ public:
// Leon options
bool hasUmacSmac() const { return HasUmacSmac; }
bool hasLeonCasa() const { return HasLeonCasa; }
+ bool hasPWRPSR() const { return HasPWRPSR; }
bool insertNOPLoad() const { return InsertNOPLoad; }
bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
bool detectRoundChange() const { return DetectRoundChange; }
Added: llvm/trunk/test/MC/Sparc/leon-pwrpsr-instruction.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/leon-pwrpsr-instruction.s?rev=343202&view=auto
==============================================================================
--- llvm/trunk/test/MC/Sparc/leon-pwrpsr-instruction.s (added)
+++ llvm/trunk/test/MC/Sparc/leon-pwrpsr-instruction.s Thu Sep 27 05:34:48 2018
@@ -0,0 +1,10 @@
+! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s
+
+ ! CHECK: pwr %g0, 0, %psr ! encoding: [0x83,0x88,0x20,0x00]
+ pwr 0, %psr
+
+ ! CHECK: pwr %g0, %l7, %psr ! encoding: [0x83,0x88,0x00,0x17]
+ pwr %l7, %psr
+
+ ! CHECK: pwr %g0, 32, %psr ! encoding: [0x83,0x88,0x20,0x20]
+ pwr 32, %psr
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