[lld] r343144 - [AArch64] Fix range check of R_AARCH64_TLSLE_ADD_TPREL_HI12

[Ryan Prichard via llvm-commits]

Author: rprichard
Date: Wed Sep 26 13:50:38 2018
New Revision: 343144

URL: http://llvm.org/viewvc/llvm-project?rev=343144&view=rev
Log:
[AArch64] Fix range check of R_AARCH64_TLSLE_ADD_TPREL_HI12

Summary:
An AArch64 LE relocation is a positive ("variant 1") offset. This
relocation is used to write the upper 12 bits of a 24-bit offset into an
add instruction:

    add x0, x0, :tprel_hi12:v1

The comment in the ARM docs for R_AARCH64_TLSLE_ADD_TPREL_HI12 is:

"Set an ADD immediate field to bits [23:12] of X; check 0 <= X < 2^24."

Reviewers: javed.absar, espindola, ruiu, peter.smith, zatrazz

Reviewed By: ruiu

Subscribers: emaste, arichardson, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D52525

Modified:
    lld/trunk/ELF/Arch/AArch64.cpp
    lld/trunk/test/ELF/aarch64-tls-le.s

Modified: lld/trunk/ELF/Arch/AArch64.cpp
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Arch/AArch64.cpp?rev=343144&r1=343143&r2=343144&view=diff
==============================================================================
--- lld/trunk/ELF/Arch/AArch64.cpp (original)
+++ lld/trunk/ELF/Arch/AArch64.cpp Wed Sep 26 13:50:38 2018
@@ -346,7 +346,7 @@ void AArch64::relocateOne(uint8_t *Loc,
     or32le(Loc, (Val & 0xFFFC) << 3);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
-    checkInt(Loc, Val, 24, Type);
+    checkUInt(Loc, Val, 24, Type);
     or32AArch64Imm(Loc, Val >> 12);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:

Modified: lld/trunk/test/ELF/aarch64-tls-le.s
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/aarch64-tls-le.s?rev=343144&r1=343143&r2=343144&view=diff
==============================================================================
--- lld/trunk/test/ELF/aarch64-tls-le.s (original)
+++ lld/trunk/test/ELF/aarch64-tls-le.s Wed Sep 26 13:50:38 2018
@@ -13,6 +13,9 @@ _start:
  mrs x0, TPIDR_EL0
  add x0, x0, :tprel_hi12:v1
  add x0, x0, :tprel_lo12_nc:v1
+ mrs x0, TPIDR_EL0
+ add x0, x0, :tprel_hi12:v2
+ add x0, x0, :tprel_lo12_nc:v2
 
 # TCB size = 0x16 and foo is first element from TLS register.
 #CHECK: Disassembly of section .text:
@@ -20,12 +23,26 @@ _start:
 #CHECK:  210000: 40 d0 3b d5     mrs     x0, TPIDR_EL0
 #CHECK:  210004: 00 00 40 91     add     x0, x0, #0, lsl #12
 #CHECK:  210008: 00 40 00 91     add     x0, x0, #16
+#CHECK:  21000c: 40 d0 3b d5     mrs     x0, TPIDR_EL0
+#CHECK:  210010: 00 fc 7f 91     add     x0, x0, #4095, lsl #12
+#CHECK:  210014: 00 e0 3f 91     add     x0, x0, #4088
 
-.type   v1, at object
 .section        .tbss,"awT", at nobits
+
+.type   v1, at object
 .globl  v1
 .p2align 2
 v1:
 .word  0
 .size  v1, 4
 
+# The current offset from the thread pointer is 20. Raise it to just below the
+# 24-bit limit.
+.space (0xfffff8 - 20)
+
+.type   v2, at object
+.globl  v2
+.p2align 2
+v2:
+.word  0
+.size  v2, 4