[PATCH] D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

The warning seem to be plain wrong.  The warning claims that

  warning: SubRegIndex SystemZ::subreg_h64 and SystemZ::subreg_h32 compose ambiguously as SystemZ::subreg_hh32 or SystemZ::subreg_h32

This is based on `V0`: `subreg_h64(V0) = F0D`, `subreg_h32(F0D) = F0S`. So the composition (and `subreg_hh32`, user-defined as that composition) maps `V0` to `F0S`.  Now `subreg_h32(V0) = F0S`, so for `V0` these two indeed agree. This is the cause for the warning. 
However, for `F0Q`, `subreg_h32(subreg_h64(F0Q)) = subreg_h32(F0D) = F0S`, while `subreg_h32(F0Q) = F2S`. So, while these compositions agree on at least one register, they are not equal in general.

For illustration, here are all subregs as maps Register->Register, where subreg: R -> R:subreg.

  subreg_h64: { V0->F0D V1->F1D V2->F2D V3->F3D V4->F4D V5->F5D V6->F6D V7->F7D
                V8->F8D V9->F9D V10->F10D V11->F11D V12->F12D V13->F13D V14->F14D V15->F15D
                V16->F16D V17->F17D V18->F18D V19->F19D V20->F20D V21->F21D V22->F22D V23->F23D
                V24->F24D V25->F25D V26->F26D V27->F27D V28->F28D V29->F29D V30->F30D V31->F31D
                F0Q->F0D F1Q->F1D F4Q->F4D F5Q->F5D F8Q->F8D F9Q->F9D F12Q->F12D F13Q->F13D
                R0Q->R0D R2Q->R2D R4Q->R4D R6Q->R6D R8Q->R8D R10Q->R10D R12Q->R12D R14Q->R14D }
  subreg_h32: { V0->F0S V1->F1S V2->F2S V3->F3S V4->F4S V5->F5S V6->F6S V7->F7S
                V8->F8S V9->F9S V10->F10S V11->F11S V12->F12S V13->F13S V14->F14S V15->F15S
                V16->F16S V17->F17S V18->F18S V19->F19S V20->F20S V21->F21S V22->F22S V23->F23S
                V24->F24S V25->F25S V26->F26S V27->F27S V28->F28S V29->F29S V30->F30S V31->F31S
                F0D->F0S F1D->F1S F2D->F2S F3D->F3S F4D->F4S F5D->F5S F6D->F6S F7D->F7S
                F8D->F8S F9D->F9S F10D->F10S F11D->F11S F12D->F12S F13D->F13S F14D->F14S F15D->F15S
                F16D->F16S F17D->F17S F18D->F18S F19D->F19S F20D->F20S F21D->F21S F22D->F22S F23D->F23S
                F24D->F24S F25D->F25S F26D->F26S F27D->F27S F28D->F28S F29D->F29S F30D->F30S F31D->F31S
                F0Q->F2S F1Q->F3S F4Q->F6S F5Q->F7S F8Q->F10S F9Q->F11S F12Q->F14S F13Q->F15S
                R0D->R0H R1D->R1H R2D->R2H R3D->R3H R4D->R4H R5D->R5H R6D->R6H R7D->R7H
                R8D->R8H R9D->R9H R10D->R10H R11D->R11H R12D->R12H R13D->R13H R14D->R14H R15D->R15H
                R0Q->R1H R2Q->R3H R4Q->R5H R6Q->R7H R8Q->R9H R10Q->R11H R12Q->R13H R14Q->R15H }
  subreg_l64: { F0Q->F2D F1Q->F3D F4Q->F6D F5Q->F7D F8Q->F10D F9Q->F11D F12Q->F14D F13Q->F15D
                R0Q->R1D R2Q->R3D R4Q->R5D R6Q->R7D R8Q->R9D R10Q->R11D R12Q->R13D R14Q->R15D }
  subreg_hh32: { F0Q->F0S F1Q->F1S F4Q->F4S F5Q->F5S F8Q->F8S F9Q->F9S F12Q->F12S F13Q->F13S
                 R0Q->R0H R2Q->R2H R4Q->R4H R6Q->R6H R8Q->R8H R10Q->R10H R12Q->R12H R14Q->R14H }
  subreg_l32: { R0D->R0L R1D->R1L R2D->R2L R3D->R3L R4D->R4L R5D->R5L R6D->R6L R7D->R7L
                R8D->R8L R9D->R9L R10D->R10L R11D->R11L R12D->R12L R13D->R13L R14D->R14L R15D->R15L
                R0Q->R1L R2Q->R3L R4Q->R5L R6Q->R7L R8Q->R9L R10Q->R11L R12Q->R13L R14Q->R15L }
  subreg_hl32: { R0Q->R0L R2Q->R2L R4Q->R4L R6Q->R6L R8Q->R8L R10Q->R10L R12Q->R12L R14Q->R14L }


Repository:
  rL LLVM

https://reviews.llvm.org/D50977