[llvm] r343107 - [CodeGen] Always print register ties in MI::dump()

Francis Visoiu Mistrih via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 26 06:33:09 PDT 2018 

Author: thegameg
Date: Wed Sep 26 06:33:09 2018
New Revision: 343107

URL: http://llvm.org/viewvc/llvm-project?rev=343107&view=rev
Log:
[CodeGen] Always print register ties in MI::dump()

It was the case when calling MO::dump(), but MI::dump() was still
depending on hasComplexRegisterTies().

The MIR output is not affected.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
    llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir
    llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=343107&r1=343106&r2=343107&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Sep 26 06:33:09 2018
@@ -1466,7 +1466,7 @@ void MachineInstr::print(raw_ostream &OS
     assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
 
   SmallBitVector PrintedTypes(8);
-  bool ShouldPrintRegisterTies = hasComplexRegisterTies();
+  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
   auto getTiedOperandIdx = [&](unsigned OpIdx) {
     if (!ShouldPrintRegisterTies)
       return 0U;

Modified: llvm/trunk/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir?rev=343107&r1=343106&r2=343107&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir Wed Sep 26 06:33:09 2018
@@ -6,7 +6,7 @@
 name: func
 body: |
   bb.0:
-    ; CHECK: SU(0): %0:fpr128 = AESErr undef $q0, undef $q1
+    ; CHECK: SU(0): %0:fpr128 = AESErr undef $q0(tied-def 0), undef $q1
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES:    SU(1): Ord  Latency=0 Cluster
@@ -14,7 +14,7 @@ body: |
     %0:fpr128 = AESErr undef $q0, undef $q1
     %1:fpr128 = AESMCrrTied %0
 
-    ; CHECK: SU(2): %2:fpr128 = AESErr undef $q2, undef $q3
+    ; CHECK: SU(2): %2:fpr128 = AESErr undef $q2(tied-def 0), undef $q3
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES:    SU(3): Ord  Latency=0 Cluster
@@ -22,7 +22,7 @@ body: |
     %2:fpr128 = AESErr undef $q2, undef $q3
     %3:fpr128 = AESMCrr %2
 
-    ; CHECK: SU(4): %4:fpr128 = AESErr %1:fpr128, undef $q4
+    ; CHECK: SU(4): %4:fpr128 = AESErr %1:fpr128(tied-def 0), undef $q4
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES-NOT: SU({{.*}}): Ord
@@ -31,7 +31,7 @@ body: |
     %4:fpr128 = AESErr %1, undef $q4
     %5:fpr128 = EORv16i8 %4, undef $q5
 
-    ; CHECK: SU(6): %6:fpr128 = AESDrr undef $q0, undef $q1
+    ; CHECK: SU(6): %6:fpr128 = AESDrr undef $q0(tied-def 0), undef $q1
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES:    SU(7): Ord  Latency=0 Cluster
@@ -39,7 +39,7 @@ body: |
     %6:fpr128 = AESDrr undef $q0, undef $q1
     %7:fpr128 = AESIMCrrTied %6
 
-    ; CHECK: SU(8): %8:fpr128 = AESDrr undef $q2, undef $q3
+    ; CHECK: SU(8): %8:fpr128 = AESDrr undef $q2(tied-def 0), undef $q3
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES:    SU(9): Ord  Latency=0 Cluster
@@ -47,7 +47,7 @@ body: |
     %8:fpr128 = AESDrr undef $q2, undef $q3
     %9:fpr128 = AESIMCrr %8
 
-    ; CHECK: SU(10): %10:fpr128 = AESDrr %7:fpr128, undef $q0
+    ; CHECK: SU(10): %10:fpr128 = AESDrr %7:fpr128(tied-def 0), undef $q0
     ; CHECK: Successors:
     ; NOFUSE-NOT: SU({{.*}}): Ord
     ; FUSEAES-NOT: SU({{.*}}): Ord

Modified: llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir?rev=343107&r1=343106&r2=343107&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir Wed Sep 26 06:33:09 2018
@@ -92,7 +92,7 @@
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(18):   %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, $noreg
+# CHECK:       SU(18):   %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr(tied-def 0), %20:rgpr(tied-def 1), 14, $noreg
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 7
 # CHECK_R52:   Latency    : 4

Modified: llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir?rev=343107&r1=343106&r2=343107&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir Wed Sep 26 06:33:09 2018
@@ -58,7 +58,7 @@
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, $noreg, $noreg
+# CHECK:       SU(11):   %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), %14:gprnopc(tied-def 1), 14, $noreg, $noreg
 # CHECK_SWIFT: Latency    : 7
 # CHECK_A9:    Latency    : 3
 # CHECK_R52:   Latency    : 4

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