[PATCH] D52426: [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/extract-bits.ll:5797
+; X64-BMI1NOTBMBMI2-NEXT:    movl $2581, %eax # imm = 0xA15
+; X64-BMI1NOTBMBMI2-NEXT:    bextrl %eax, %edi, %eax
+; X64-BMI1NOTBMBMI2-NEXT:    shll $2, %eax
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lebedev.ri wrote:
> craig.topper wrote:
> > This is not an improvement. We traded a shift right plus an and for a move immediate, a 2 uop bextr, and a shift left. So we went from 2 uops to 4. At least on Haswell.
> Aha. So the D52293 has the same problem, obviously.
> Is adding `FeatureSlowBEXTR` the way forward?
It's still an increase in instruction even on AMD in the BMI1 case. We still went from 2 uops to 3 uops. We'd only be ok with BEXTRI TBM instruction.

In the case from PR38938 we were able to fold the shl into an addressing calculation which made it beneficial.


Repository:
  rL LLVM

https://reviews.llvm.org/D52426