[PATCH] D52469: AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns

[Tom Stellard via Phabricator via llvm-commits]

tstellar created this revision.
tstellar added reviewers: arsenm, nhaehnle.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.

This is essentially NFC, because the complex pattern used for these patterns
will fail on non-CI, but this makes the pattern consistent with other CI
smrd patterns.  It is also a performance improvement, because the pattern
will now fail earlier on non-CI.


Repository:
  rL LLVM

https://reviews.llvm.org/D52469

Files:
  lib/Target/AMDGPU/SMInstructions.td


Index: lib/Target/AMDGPU/SMInstructions.td
===================================================================
--- lib/Target/AMDGPU/SMInstructions.td
+++ lib/Target/AMDGPU/SMInstructions.td
@@ -777,7 +777,7 @@
 class SMLoad_Pattern_ci <string Instr, ValueType vt> : GCNPat <
   (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
   (!cast<InstSI>(Instr) $sbase, $offset, (as_i1imm $glc))> {
-  let OtherPredicates = [isCI]; // should this be isCIOnly?
+  let OtherPredicates = [isCIOnly];
 }
 
 def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORD_IMM_ci", i32>;


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