[PATCH] D52410: Use TRI->regsOverlap() in MachineBasicBlock::computeRegisterLiveness

Mon Sep 24 07:21:32 PDT 2018

uabelho added a comment.

I would like to create a testcase exposing that we actually fix a bug when we use regsOverlap() instead of MCSubRegIterator, but then I think I need help.

In https://reviews.llvm.org/D51348 Matt suggested it can be triggered in an "AMDGPU testcase where VCC_LO or VCC_HI is defined and VCC is the live out".
I'm not sure about this though. I don't know AMDGPU or how computeRegisterLivenessis used there, but just by looking at the definition of VCC I'm not sure
it's enough to trigger the problem:

def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,

  DwarfRegAlias<VCC_LO> {

Since both VCC_LO and VCC_HI are sub registers of VCC I think the old MCSubRegIterator code works?

What we would need would be some register VCC_X that is made up of both VCC_LO or VCC_HI _and_ some other part so it overlaps/aliases VCC, but it's not
a sub register of VCC.

Repository:
  rL LLVM

https://reviews.llvm.org/D52410