[PATCH] D46423: [WIP, RISCV] Support .option relax and .option norelax

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

In https://reviews.llvm.org/D46423#1243098, @lewis-revill wrote:

> Just an update to my previous comment, I realised you were right @asb since we don't update the AsmBackend's SubtargetInfo anymore, so `getFeatureBits()[RISCV::FeatureRelax]` will still be true after parsing based on the `-mattr=relax`. I'm looking into potentially using only the `ForceRelocs` variable for relocation behaviour and trying to set this lazily when we parse an instruction that might be relaxed in a relaxable section to cover the case you mentioned. I'll update whether I think this is possible ASAP.


Thinking about it more, it's probably not worth worrying about the case where -mrelax is passed but .option norelax occurs early on in assembly. Or at least, it's a secondary concern to achieving the following (let me know if you think the desirable behaviour is something different):

- -mattr=+relax: Set FeatureRelax and ForceReloc. Even if .option norelax is encountered when parsing assembly, ForceReloc stays set.
- -mattr=-relax. FeatureRelax and ForceReloc are false. If .option relax is encountered then set FeatureRelax and ForceReloc. ForceReloc will not be unset, even if .option norelax is encountered.
- The above should happen both for the assembler and the 'direct codegen' codepath.

I think the direction you suggest with ForceRelocs should enable this, and probably makes the whole thing much easier to understand.


Repository:
  rL LLVM

https://reviews.llvm.org/D46423