[PATCH] D52358: [X86][Sched] Add zero idiom sched data to the SNB model.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86SchedSandyBridge.td:37
 let SchedModel = SandyBridgeModel in {
 
 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
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Add PRF data as well ?


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Comment at: lib/Target/X86/X86SchedSandyBridge.td:1143
+// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
+// section 9.8 "Register allocation and renaming".
+// These can be investigated with llvm-exegesis, e.g.
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You might want to avoid "9.8" - Agner has a tendency to reorder chapter numbers....

Section "Sandy Bridge and Ivy Bridge Pipeline": "Register allocation and renaming"

might be better.


Repository:
  rL LLVM

https://reviews.llvm.org/D52358