[llvm] r342595 - [x86] add test for 256-bit andn (PR37749); NFC

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 19 15:00:56 PDT 2018


Author: spatel
Date: Wed Sep 19 15:00:56 2018
New Revision: 342595

URL: http://llvm.org/viewvc/llvm-project?rev=342595&view=rev
Log:
[x86] add test for 256-bit andn (PR37749); NFC

Modified:
    llvm/trunk/test/CodeGen/X86/avx-logic.ll

Modified: llvm/trunk/test/CodeGen/X86/avx-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-logic.ll?rev=342595&r1=342594&r2=342595&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-logic.ll Wed Sep 19 15:00:56 2018
@@ -335,6 +335,35 @@ define <8 x i32> @and_disguised_i8_elts(
   ret <8 x i32> %t
 }
 
+define <8 x i32> @andn_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
+; AVX1-LABEL: andn_disguised_i8_elts:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT:    vpaddd %xmm3, %xmm4, %xmm3
+; AVX1-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX1-NEXT:    vandnps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm3
+; AVX1-NEXT:    vpaddd %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; INT256-LABEL: andn_disguised_i8_elts:
+; INT256:       # %bb.0:
+; INT256-NEXT:    vpaddd %ymm0, %ymm1, %ymm0
+; INT256-NEXT:    vpandn {{.*}}(%rip), %ymm0, %ymm0
+; INT256-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
+; INT256-NEXT:    retq
+  %add = add <8 x i32> %y, %x
+  %neg = and <8 x i32> %add, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
+  %and = xor <8 x i32> %neg, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
+  %add1 = add <8 x i32> %and, %z
+  ret <8 x i32> %add1
+}
+
 define <8 x i32> @or_disguised_i8_elts(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
 ; AVX1-LABEL: or_disguised_i8_elts:
 ; AVX1:       # %bb.0:




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